xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSchedRocket.td (revision f126890ac5386406dadf7c4cfa9566cbb56537c5)
1//==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9// ===---------------------------------------------------------------------===//
10// The following definitions describe the simpler per-operand machine model.
11// This works with MachineScheduler. See MCSchedule.h for details.
12
13// Rocket machine model for scheduling and other instruction cost heuristics.
14def RocketModel : SchedMachineModel {
15  let MicroOpBufferSize = 0; // Rocket is in-order.
16  let IssueWidth = 1;        // 1 micro-op is dispatched per cycle.
17  let LoadLatency = 3;
18  let MispredictPenalty = 3;
19  let CompleteModel = false;
20  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
21                             HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
22                             HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
23                             HasStdExtZkr, HasVInstructions, HasVInstructionsI64];
24}
25
26//===----------------------------------------------------------------------===//
27// Define each kind of processor resource and number available.
28
29// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
30// Rocket is in-order.
31
32let BufferSize = 0 in {
33def RocketUnitALU        : ProcResource<1>; // Int ALU
34def RocketUnitIMul       : ProcResource<1>; // Int Multiply
35def RocketUnitMem        : ProcResource<1>; // Load/Store
36def RocketUnitB          : ProcResource<1>; // Branch
37
38def RocketUnitFPALU      : ProcResource<1>; // FP ALU
39}
40
41let BufferSize = 1 in {
42def RocketUnitIDiv       : ProcResource<1>; // Int Division
43def RocketUnitFPDivSqrt  : ProcResource<1>; // FP Divide/Sqrt
44}
45
46//===----------------------------------------------------------------------===//
47
48let SchedModel = RocketModel in {
49
50// Branching
51def : WriteRes<WriteJmp, [RocketUnitB]>;
52def : WriteRes<WriteJal, [RocketUnitB]>;
53def : WriteRes<WriteJalr, [RocketUnitB]>;
54
55// Integer arithmetic and logic
56def : WriteRes<WriteIALU32, [RocketUnitALU]>;
57def : WriteRes<WriteIALU, [RocketUnitALU]>;
58def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
59def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
60def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
61def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
62
63// Integer multiplication
64let Latency = 4 in {
65def : WriteRes<WriteIMul, [RocketUnitIMul]>;
66def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
67}
68
69// Integer division
70// Worst case latency is used.
71def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
72  let Latency = 34;
73  let ResourceCycles = [34];
74}
75def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
76  let Latency = 33;
77  let ResourceCycles = [33];
78}
79
80// Memory
81def : WriteRes<WriteSTB, [RocketUnitMem]>;
82def : WriteRes<WriteSTH, [RocketUnitMem]>;
83def : WriteRes<WriteSTW, [RocketUnitMem]>;
84def : WriteRes<WriteSTD, [RocketUnitMem]>;
85def : WriteRes<WriteFST32, [RocketUnitMem]>;
86def : WriteRes<WriteFST64, [RocketUnitMem]>;
87
88let Latency = 3 in {
89def : WriteRes<WriteLDB, [RocketUnitMem]>;
90def : WriteRes<WriteLDH, [RocketUnitMem]>;
91}
92
93let Latency = 2 in {
94def : WriteRes<WriteLDW, [RocketUnitMem]>;
95def : WriteRes<WriteLDD, [RocketUnitMem]>;
96def : WriteRes<WriteFLD32, [RocketUnitMem]>;
97def : WriteRes<WriteFLD64, [RocketUnitMem]>;
98
99// Atomic memory
100def : WriteRes<WriteAtomicW, [RocketUnitMem]>;
101def : WriteRes<WriteAtomicD, [RocketUnitMem]>;
102
103def : WriteRes<WriteAtomicLDW, [RocketUnitMem]>;
104def : WriteRes<WriteAtomicLDD, [RocketUnitMem]>;
105}
106
107def : WriteRes<WriteAtomicSTW, [RocketUnitMem]>;
108def : WriteRes<WriteAtomicSTD, [RocketUnitMem]>;
109
110// Single precision.
111let Latency = 4 in {
112def : WriteRes<WriteFAdd32, [RocketUnitFPALU]>;
113def : WriteRes<WriteFSGNJ32, [RocketUnitFPALU]>;
114def : WriteRes<WriteFMinMax32, [RocketUnitFPALU]>;
115}
116
117// Double precision
118let Latency = 6 in {
119def : WriteRes<WriteFAdd64, [RocketUnitFPALU]>;
120def : WriteRes<WriteFSGNJ64, [RocketUnitFPALU]>;
121def : WriteRes<WriteFMinMax64, [RocketUnitFPALU]>;
122}
123
124// Conversions
125let Latency = 2 in {
126def : WriteRes<WriteFCvtI32ToF32, [RocketUnitFPALU]>;
127def : WriteRes<WriteFCvtI32ToF64, [RocketUnitFPALU]>;
128def : WriteRes<WriteFCvtI64ToF32, [RocketUnitFPALU]>;
129def : WriteRes<WriteFCvtI64ToF64, [RocketUnitFPALU]>;
130def : WriteRes<WriteFCvtF32ToI32, [RocketUnitFPALU]>;
131def : WriteRes<WriteFCvtF32ToI64, [RocketUnitFPALU]>;
132def : WriteRes<WriteFCvtF64ToI32, [RocketUnitFPALU]>;
133def : WriteRes<WriteFCvtF64ToI64, [RocketUnitFPALU]>;
134def : WriteRes<WriteFCvtF32ToF64, [RocketUnitFPALU]>;
135def : WriteRes<WriteFCvtF64ToF32, [RocketUnitFPALU]>;
136
137def : WriteRes<WriteFClass32, [RocketUnitFPALU]>;
138def : WriteRes<WriteFClass64, [RocketUnitFPALU]>;
139def : WriteRes<WriteFCmp32, [RocketUnitFPALU]>;
140def : WriteRes<WriteFCmp64, [RocketUnitFPALU]>;
141def : WriteRes<WriteFMovF32ToI32, [RocketUnitFPALU]>;
142def : WriteRes<WriteFMovI32ToF32, [RocketUnitFPALU]>;
143def : WriteRes<WriteFMovF64ToI64, [RocketUnitFPALU]>;
144def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>;
145}
146
147// FP multiplication
148let Latency = 5 in {
149def : WriteRes<WriteFMul32, [RocketUnitFPALU]>;
150def : WriteRes<WriteFMA32, [RocketUnitFPALU]>;
151}
152
153let Latency = 7 in {
154def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;
155def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
156}
157
158// FP division
159// FP division unit on Rocket is not pipelined, so set resource cycles to latency.
160let Latency = 20, ResourceCycles = [20] in {
161def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
162def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
163}
164
165// FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
166def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
167                                                      let ResourceCycles = [20]; }
168def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
169                                                      let ResourceCycles = [25]; }
170
171// Others
172def : WriteRes<WriteCSR, []>;
173def : WriteRes<WriteNop, []>;
174
175def : InstRW<[WriteIALU], (instrs COPY)>;
176
177//===----------------------------------------------------------------------===//
178// Bypass and advance
179def : ReadAdvance<ReadJmp, 0>;
180def : ReadAdvance<ReadJalr, 0>;
181def : ReadAdvance<ReadCSR, 0>;
182def : ReadAdvance<ReadStoreData, 0>;
183def : ReadAdvance<ReadMemBase, 0>;
184def : ReadAdvance<ReadIALU, 0>;
185def : ReadAdvance<ReadIALU32, 0>;
186def : ReadAdvance<ReadShiftImm, 0>;
187def : ReadAdvance<ReadShiftImm32, 0>;
188def : ReadAdvance<ReadShiftReg, 0>;
189def : ReadAdvance<ReadShiftReg32, 0>;
190def : ReadAdvance<ReadIDiv, 0>;
191def : ReadAdvance<ReadIDiv32, 0>;
192def : ReadAdvance<ReadIMul, 0>;
193def : ReadAdvance<ReadIMul32, 0>;
194def : ReadAdvance<ReadAtomicWA, 0>;
195def : ReadAdvance<ReadAtomicWD, 0>;
196def : ReadAdvance<ReadAtomicDA, 0>;
197def : ReadAdvance<ReadAtomicDD, 0>;
198def : ReadAdvance<ReadAtomicLDW, 0>;
199def : ReadAdvance<ReadAtomicLDD, 0>;
200def : ReadAdvance<ReadAtomicSTW, 0>;
201def : ReadAdvance<ReadAtomicSTD, 0>;
202def : ReadAdvance<ReadFStoreData, 0>;
203def : ReadAdvance<ReadFMemBase, 0>;
204def : ReadAdvance<ReadFAdd32, 0>;
205def : ReadAdvance<ReadFAdd64, 0>;
206def : ReadAdvance<ReadFMul32, 0>;
207def : ReadAdvance<ReadFMul64, 0>;
208def : ReadAdvance<ReadFMA32, 0>;
209def : ReadAdvance<ReadFMA64, 0>;
210def : ReadAdvance<ReadFDiv32, 0>;
211def : ReadAdvance<ReadFDiv64, 0>;
212def : ReadAdvance<ReadFSqrt32, 0>;
213def : ReadAdvance<ReadFSqrt64, 0>;
214def : ReadAdvance<ReadFCmp32, 0>;
215def : ReadAdvance<ReadFCmp64, 0>;
216def : ReadAdvance<ReadFSGNJ32, 0>;
217def : ReadAdvance<ReadFSGNJ64, 0>;
218def : ReadAdvance<ReadFMinMax32, 0>;
219def : ReadAdvance<ReadFMinMax64, 0>;
220def : ReadAdvance<ReadFCvtF32ToI32, 0>;
221def : ReadAdvance<ReadFCvtF32ToI64, 0>;
222def : ReadAdvance<ReadFCvtF64ToI32, 0>;
223def : ReadAdvance<ReadFCvtF64ToI64, 0>;
224def : ReadAdvance<ReadFCvtI32ToF32, 0>;
225def : ReadAdvance<ReadFCvtI32ToF64, 0>;
226def : ReadAdvance<ReadFCvtI64ToF32, 0>;
227def : ReadAdvance<ReadFCvtI64ToF64, 0>;
228def : ReadAdvance<ReadFCvtF32ToF64, 0>;
229def : ReadAdvance<ReadFCvtF64ToF32, 0>;
230def : ReadAdvance<ReadFMovF32ToI32, 0>;
231def : ReadAdvance<ReadFMovI32ToF32, 0>;
232def : ReadAdvance<ReadFMovF64ToI64, 0>;
233def : ReadAdvance<ReadFMovI64ToF64, 0>;
234def : ReadAdvance<ReadFClass32, 0>;
235def : ReadAdvance<ReadFClass64, 0>;
236
237//===----------------------------------------------------------------------===//
238// Unsupported extensions
239defm : UnsupportedSchedV;
240defm : UnsupportedSchedZba;
241defm : UnsupportedSchedZbb;
242defm : UnsupportedSchedZbc;
243defm : UnsupportedSchedZbs;
244defm : UnsupportedSchedZbkb;
245defm : UnsupportedSchedZbkx;
246defm : UnsupportedSchedZfa;
247defm : UnsupportedSchedZfh;
248defm : UnsupportedSchedSFB;
249}
250