1//==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// ===---------------------------------------------------------------------===// 10// The following definitions describe the simpler per-operand machine model. 11// This works with MachineScheduler. See MCSchedule.h for details. 12 13// Rocket machine model for scheduling and other instruction cost heuristics. 14def RocketModel : SchedMachineModel { 15 let MicroOpBufferSize = 0; // Rocket is in-order. 16 let IssueWidth = 1; // 1 micro-op is dispatched per cycle. 17 let LoadLatency = 3; 18 let MispredictPenalty = 3; 19 let CompleteModel = false; 20 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, 21 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, 22 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, 23 HasVInstructions, HasVInstructionsI64]; 24} 25 26//===----------------------------------------------------------------------===// 27// Define each kind of processor resource and number available. 28 29// Modeling each pipeline as a ProcResource using the BufferSize = 0 since 30// Rocket is in-order. 31 32let BufferSize = 0 in { 33def RocketUnitALU : ProcResource<1>; // Int ALU 34def RocketUnitIMul : ProcResource<1>; // Int Multiply 35def RocketUnitMem : ProcResource<1>; // Load/Store 36def RocketUnitB : ProcResource<1>; // Branch 37 38def RocketUnitFPALU : ProcResource<1>; // FP ALU 39} 40 41let BufferSize = 1 in { 42def RocketUnitIDiv : ProcResource<1>; // Int Division 43def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt 44} 45 46//===----------------------------------------------------------------------===// 47 48let SchedModel = RocketModel in { 49 50// Branching 51def : WriteRes<WriteJmp, [RocketUnitB]>; 52def : WriteRes<WriteJal, [RocketUnitB]>; 53def : WriteRes<WriteJalr, [RocketUnitB]>; 54def : WriteRes<WriteJmpReg, [RocketUnitB]>; 55 56// Integer arithmetic and logic 57def : WriteRes<WriteIALU32, [RocketUnitALU]>; 58def : WriteRes<WriteIALU, [RocketUnitALU]>; 59def : WriteRes<WriteShiftImm32, [RocketUnitALU]>; 60def : WriteRes<WriteShiftImm, [RocketUnitALU]>; 61def : WriteRes<WriteShiftReg32, [RocketUnitALU]>; 62def : WriteRes<WriteShiftReg, [RocketUnitALU]>; 63 64// Integer multiplication 65let Latency = 4 in { 66def : WriteRes<WriteIMul, [RocketUnitIMul]>; 67def : WriteRes<WriteIMul32, [RocketUnitIMul]>; 68} 69 70// Integer division 71// Worst case latency is used. 72def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> { 73 let Latency = 34; 74 let ResourceCycles = [34]; 75} 76def : WriteRes<WriteIDiv, [RocketUnitIDiv]> { 77 let Latency = 33; 78 let ResourceCycles = [33]; 79} 80 81// Memory 82def : WriteRes<WriteSTB, [RocketUnitMem]>; 83def : WriteRes<WriteSTH, [RocketUnitMem]>; 84def : WriteRes<WriteSTW, [RocketUnitMem]>; 85def : WriteRes<WriteSTD, [RocketUnitMem]>; 86def : WriteRes<WriteFST32, [RocketUnitMem]>; 87def : WriteRes<WriteFST64, [RocketUnitMem]>; 88 89let Latency = 3 in { 90def : WriteRes<WriteLDB, [RocketUnitMem]>; 91def : WriteRes<WriteLDH, [RocketUnitMem]>; 92} 93 94let Latency = 2 in { 95def : WriteRes<WriteLDW, [RocketUnitMem]>; 96def : WriteRes<WriteLDWU, [RocketUnitMem]>; 97def : WriteRes<WriteLDD, [RocketUnitMem]>; 98def : WriteRes<WriteFLD32, [RocketUnitMem]>; 99def : WriteRes<WriteFLD64, [RocketUnitMem]>; 100 101// Atomic memory 102def : WriteRes<WriteAtomicW, [RocketUnitMem]>; 103def : WriteRes<WriteAtomicD, [RocketUnitMem]>; 104 105def : WriteRes<WriteAtomicLDW, [RocketUnitMem]>; 106def : WriteRes<WriteAtomicLDD, [RocketUnitMem]>; 107} 108 109def : WriteRes<WriteAtomicSTW, [RocketUnitMem]>; 110def : WriteRes<WriteAtomicSTD, [RocketUnitMem]>; 111 112// Single precision. 113let Latency = 4 in { 114def : WriteRes<WriteFALU32, [RocketUnitFPALU]>; 115def : WriteRes<WriteFSGNJ32, [RocketUnitFPALU]>; 116def : WriteRes<WriteFMinMax32, [RocketUnitFPALU]>; 117} 118 119// Double precision 120let Latency = 6 in { 121def : WriteRes<WriteFALU64, [RocketUnitFPALU]>; 122def : WriteRes<WriteFSGNJ64, [RocketUnitFPALU]>; 123def : WriteRes<WriteFMinMax64, [RocketUnitFPALU]>; 124} 125 126// Conversions 127let Latency = 2 in { 128def : WriteRes<WriteFCvtI32ToF32, [RocketUnitFPALU]>; 129def : WriteRes<WriteFCvtI32ToF64, [RocketUnitFPALU]>; 130def : WriteRes<WriteFCvtI64ToF32, [RocketUnitFPALU]>; 131def : WriteRes<WriteFCvtI64ToF64, [RocketUnitFPALU]>; 132def : WriteRes<WriteFCvtF32ToI32, [RocketUnitFPALU]>; 133def : WriteRes<WriteFCvtF32ToI64, [RocketUnitFPALU]>; 134def : WriteRes<WriteFCvtF64ToI32, [RocketUnitFPALU]>; 135def : WriteRes<WriteFCvtF64ToI64, [RocketUnitFPALU]>; 136def : WriteRes<WriteFCvtF32ToF64, [RocketUnitFPALU]>; 137def : WriteRes<WriteFCvtF64ToF32, [RocketUnitFPALU]>; 138 139def : WriteRes<WriteFClass32, [RocketUnitFPALU]>; 140def : WriteRes<WriteFClass64, [RocketUnitFPALU]>; 141def : WriteRes<WriteFCmp32, [RocketUnitFPALU]>; 142def : WriteRes<WriteFCmp64, [RocketUnitFPALU]>; 143def : WriteRes<WriteFMovF32ToI32, [RocketUnitFPALU]>; 144def : WriteRes<WriteFMovI32ToF32, [RocketUnitFPALU]>; 145def : WriteRes<WriteFMovF64ToI64, [RocketUnitFPALU]>; 146def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>; 147} 148 149// FP multiplication 150let Latency = 5 in { 151def : WriteRes<WriteFMul32, [RocketUnitFPALU]>; 152def : WriteRes<WriteFMA32, [RocketUnitFPALU]>; 153} 154 155let Latency = 7 in { 156def : WriteRes<WriteFMul64, [RocketUnitFPALU]>; 157def : WriteRes<WriteFMA64, [RocketUnitFPALU]>; 158} 159 160// FP division 161// FP division unit on Rocket is not pipelined, so set resource cycles to latency. 162let Latency = 20, ResourceCycles = [20] in { 163def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>; 164def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>; 165} 166 167// FP square root unit on Rocket is not pipelined, so set resource cycles to latency. 168def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20; 169 let ResourceCycles = [20]; } 170def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25; 171 let ResourceCycles = [25]; } 172 173// Others 174def : WriteRes<WriteCSR, []>; 175def : WriteRes<WriteNop, []>; 176 177def : InstRW<[WriteIALU], (instrs COPY)>; 178 179//===----------------------------------------------------------------------===// 180// Bypass and advance 181def : ReadAdvance<ReadJmp, 0>; 182def : ReadAdvance<ReadJalr, 0>; 183def : ReadAdvance<ReadCSR, 0>; 184def : ReadAdvance<ReadStoreData, 0>; 185def : ReadAdvance<ReadMemBase, 0>; 186def : ReadAdvance<ReadIALU, 0>; 187def : ReadAdvance<ReadIALU32, 0>; 188def : ReadAdvance<ReadShiftImm, 0>; 189def : ReadAdvance<ReadShiftImm32, 0>; 190def : ReadAdvance<ReadShiftReg, 0>; 191def : ReadAdvance<ReadShiftReg32, 0>; 192def : ReadAdvance<ReadIDiv, 0>; 193def : ReadAdvance<ReadIDiv32, 0>; 194def : ReadAdvance<ReadIMul, 0>; 195def : ReadAdvance<ReadIMul32, 0>; 196def : ReadAdvance<ReadAtomicWA, 0>; 197def : ReadAdvance<ReadAtomicWD, 0>; 198def : ReadAdvance<ReadAtomicDA, 0>; 199def : ReadAdvance<ReadAtomicDD, 0>; 200def : ReadAdvance<ReadAtomicLDW, 0>; 201def : ReadAdvance<ReadAtomicLDD, 0>; 202def : ReadAdvance<ReadAtomicSTW, 0>; 203def : ReadAdvance<ReadAtomicSTD, 0>; 204def : ReadAdvance<ReadFMemBase, 0>; 205def : ReadAdvance<ReadFALU32, 0>; 206def : ReadAdvance<ReadFALU64, 0>; 207def : ReadAdvance<ReadFMul32, 0>; 208def : ReadAdvance<ReadFMA32, 0>; 209def : ReadAdvance<ReadFMul64, 0>; 210def : ReadAdvance<ReadFMA64, 0>; 211def : ReadAdvance<ReadFDiv32, 0>; 212def : ReadAdvance<ReadFDiv64, 0>; 213def : ReadAdvance<ReadFSqrt32, 0>; 214def : ReadAdvance<ReadFSqrt64, 0>; 215def : ReadAdvance<ReadFCmp32, 0>; 216def : ReadAdvance<ReadFCmp64, 0>; 217def : ReadAdvance<ReadFSGNJ32, 0>; 218def : ReadAdvance<ReadFSGNJ64, 0>; 219def : ReadAdvance<ReadFMinMax32, 0>; 220def : ReadAdvance<ReadFMinMax64, 0>; 221def : ReadAdvance<ReadFCvtF32ToI32, 0>; 222def : ReadAdvance<ReadFCvtF32ToI64, 0>; 223def : ReadAdvance<ReadFCvtF64ToI32, 0>; 224def : ReadAdvance<ReadFCvtF64ToI64, 0>; 225def : ReadAdvance<ReadFCvtI32ToF32, 0>; 226def : ReadAdvance<ReadFCvtI32ToF64, 0>; 227def : ReadAdvance<ReadFCvtI64ToF32, 0>; 228def : ReadAdvance<ReadFCvtI64ToF64, 0>; 229def : ReadAdvance<ReadFCvtF32ToF64, 0>; 230def : ReadAdvance<ReadFCvtF64ToF32, 0>; 231def : ReadAdvance<ReadFMovF32ToI32, 0>; 232def : ReadAdvance<ReadFMovI32ToF32, 0>; 233def : ReadAdvance<ReadFMovF64ToI64, 0>; 234def : ReadAdvance<ReadFMovI64ToF64, 0>; 235def : ReadAdvance<ReadFClass32, 0>; 236def : ReadAdvance<ReadFClass64, 0>; 237 238//===----------------------------------------------------------------------===// 239// Unsupported extensions 240defm : UnsupportedSchedV; 241defm : UnsupportedSchedZba; 242defm : UnsupportedSchedZbb; 243defm : UnsupportedSchedZbc; 244defm : UnsupportedSchedZbs; 245defm : UnsupportedSchedZbe; 246defm : UnsupportedSchedZbf; 247defm : UnsupportedSchedZbm; 248defm : UnsupportedSchedZbp; 249defm : UnsupportedSchedZbr; 250defm : UnsupportedSchedZbt; 251defm : UnsupportedSchedZfh; 252} 253