1 //===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H 15 16 #include "llvm/CodeGen/TargetRegisterInfo.h" 17 18 #define GET_REGINFO_HEADER 19 #include "RISCVGenRegisterInfo.inc" 20 21 namespace llvm { 22 23 struct RISCVRegisterInfo : public RISCVGenRegisterInfo { 24 25 RISCVRegisterInfo(unsigned HwMode); 26 27 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 28 CallingConv::ID) const override; 29 30 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 31 32 BitVector getReservedRegs(const MachineFunction &MF) const override; 33 34 bool isConstantPhysReg(unsigned PhysReg) const override; 35 36 const uint32_t *getNoPreservedMask() const override; 37 38 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 39 unsigned FIOperandNum, 40 RegScavenger *RS = nullptr) const override; 41 42 Register getFrameRegister(const MachineFunction &MF) const override; 43 44 bool requiresRegisterScavenging(const MachineFunction &MF) const override { 45 return true; 46 } 47 48 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 49 return true; 50 } 51 52 bool trackLivenessAfterRegAlloc(const MachineFunction &) const override { 53 return true; 54 } 55 56 const TargetRegisterClass * 57 getPointerRegClass(const MachineFunction &MF, 58 unsigned Kind = 0) const override { 59 return &RISCV::GPRRegClass; 60 } 61 }; 62 } 63 64 #endif 65