10b57cec5SDimitry Andric //===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the RISCV implementation of the TargetRegisterInfo class. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #define GET_REGINFO_HEADER 190b57cec5SDimitry Andric #include "RISCVGenRegisterInfo.inc" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric namespace llvm { 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric struct RISCVRegisterInfo : public RISCVGenRegisterInfo { 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric RISCVRegisterInfo(unsigned HwMode); 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric const uint32_t *getCallPreservedMask(const MachineFunction &MF, 280b57cec5SDimitry Andric CallingConv::ID) const override; 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 310b57cec5SDimitry Andric 320b57cec5SDimitry Andric BitVector getReservedRegs(const MachineFunction &MF) const override; 33480093f4SDimitry Andric bool isAsmClobberable(const MachineFunction &MF, 34*5ffd83dbSDimitry Andric MCRegister PhysReg) const override; 350b57cec5SDimitry Andric 36*5ffd83dbSDimitry Andric bool isConstantPhysReg(MCRegister PhysReg) const override; 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric const uint32_t *getNoPreservedMask() const override; 390b57cec5SDimitry Andric 40*5ffd83dbSDimitry Andric bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, 41*5ffd83dbSDimitry Andric int &FrameIdx) const override; 42*5ffd83dbSDimitry Andric 430b57cec5SDimitry Andric void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 440b57cec5SDimitry Andric unsigned FIOperandNum, 450b57cec5SDimitry Andric RegScavenger *RS = nullptr) const override; 460b57cec5SDimitry Andric 470b57cec5SDimitry Andric Register getFrameRegister(const MachineFunction &MF) const override; 480b57cec5SDimitry Andric 490b57cec5SDimitry Andric bool requiresRegisterScavenging(const MachineFunction &MF) const override { 500b57cec5SDimitry Andric return true; 510b57cec5SDimitry Andric } 520b57cec5SDimitry Andric 530b57cec5SDimitry Andric bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 540b57cec5SDimitry Andric return true; 550b57cec5SDimitry Andric } 560b57cec5SDimitry Andric 57c14a5a88SDimitry Andric const TargetRegisterClass * 58c14a5a88SDimitry Andric getPointerRegClass(const MachineFunction &MF, 59c14a5a88SDimitry Andric unsigned Kind = 0) const override { 60c14a5a88SDimitry Andric return &RISCV::GPRRegClass; 61c14a5a88SDimitry Andric } 620b57cec5SDimitry Andric }; 630b57cec5SDimitry Andric } 640b57cec5SDimitry Andric 650b57cec5SDimitry Andric #endif 66