1*06c3fb27SDimitry Andric //===-- RISCVRegisterInfo.h - RISC-V Register Information Impl --*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 9*06c3fb27SDimitry Andric // This file contains the RISC-V implementation of the TargetRegisterInfo class. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #define GET_REGINFO_HEADER 190b57cec5SDimitry Andric #include "RISCVGenRegisterInfo.inc" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric namespace llvm { 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric struct RISCVRegisterInfo : public RISCVGenRegisterInfo { 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric RISCVRegisterInfo(unsigned HwMode); 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric const uint32_t *getCallPreservedMask(const MachineFunction &MF, 280b57cec5SDimitry Andric CallingConv::ID) const override; 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 310b57cec5SDimitry Andric 320b57cec5SDimitry Andric BitVector getReservedRegs(const MachineFunction &MF) const override; 33480093f4SDimitry Andric bool isAsmClobberable(const MachineFunction &MF, 345ffd83dbSDimitry Andric MCRegister PhysReg) const override; 350b57cec5SDimitry Andric 360b57cec5SDimitry Andric const uint32_t *getNoPreservedMask() const override; 370b57cec5SDimitry Andric 385ffd83dbSDimitry Andric bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, 395ffd83dbSDimitry Andric int &FrameIdx) const override; 405ffd83dbSDimitry Andric 41bdd1243dSDimitry Andric // Update DestReg to have the value SrcReg plus an offset. This is 42bdd1243dSDimitry Andric // used during frame layout, and we may need to ensure that if we 43bdd1243dSDimitry Andric // split the offset internally that the DestReg is always aligned, 44bdd1243dSDimitry Andric // assuming that source reg was. 45bdd1243dSDimitry Andric void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, 46bdd1243dSDimitry Andric const DebugLoc &DL, Register DestReg, Register SrcReg, 47bdd1243dSDimitry Andric StackOffset Offset, MachineInstr::MIFlag Flag, 48bdd1243dSDimitry Andric MaybeAlign RequiredAlign) const; 49bdd1243dSDimitry Andric 50bdd1243dSDimitry Andric bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 510b57cec5SDimitry Andric unsigned FIOperandNum, 520b57cec5SDimitry Andric RegScavenger *RS = nullptr) const override; 530b57cec5SDimitry Andric 54bdd1243dSDimitry Andric bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; 55bdd1243dSDimitry Andric 56bdd1243dSDimitry Andric bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 57bdd1243dSDimitry Andric 58bdd1243dSDimitry Andric bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, 59bdd1243dSDimitry Andric int64_t Offset) const override; 60bdd1243dSDimitry Andric 61bdd1243dSDimitry Andric Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, 62bdd1243dSDimitry Andric int64_t Offset) const override; 63bdd1243dSDimitry Andric 64bdd1243dSDimitry Andric void resolveFrameIndex(MachineInstr &MI, Register BaseReg, 65bdd1243dSDimitry Andric int64_t Offset) const override; 66bdd1243dSDimitry Andric 67bdd1243dSDimitry Andric int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 68bdd1243dSDimitry Andric int Idx) const override; 69bdd1243dSDimitry Andric 70bdd1243dSDimitry Andric void lowerVSPILL(MachineBasicBlock::iterator II) const; 71bdd1243dSDimitry Andric void lowerVRELOAD(MachineBasicBlock::iterator II) const; 72bdd1243dSDimitry Andric 730b57cec5SDimitry Andric Register getFrameRegister(const MachineFunction &MF) const override; 740b57cec5SDimitry Andric 750b57cec5SDimitry Andric bool requiresRegisterScavenging(const MachineFunction &MF) const override { 760b57cec5SDimitry Andric return true; 770b57cec5SDimitry Andric } 780b57cec5SDimitry Andric 790b57cec5SDimitry Andric bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 800b57cec5SDimitry Andric return true; 810b57cec5SDimitry Andric } 820b57cec5SDimitry Andric 83c14a5a88SDimitry Andric const TargetRegisterClass * 84c14a5a88SDimitry Andric getPointerRegClass(const MachineFunction &MF, 85c14a5a88SDimitry Andric unsigned Kind = 0) const override { 86c14a5a88SDimitry Andric return &RISCV::GPRRegClass; 87c14a5a88SDimitry Andric } 88fe6060f1SDimitry Andric 89fe6060f1SDimitry Andric const TargetRegisterClass * 90fe6060f1SDimitry Andric getLargestLegalSuperClass(const TargetRegisterClass *RC, 91fe6060f1SDimitry Andric const MachineFunction &) const override; 924824e7fdSDimitry Andric 934824e7fdSDimitry Andric void getOffsetOpcodes(const StackOffset &Offset, 944824e7fdSDimitry Andric SmallVectorImpl<uint64_t> &Ops) const override; 9504eeddc0SDimitry Andric 9604eeddc0SDimitry Andric unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override; 97bdd1243dSDimitry Andric 98bdd1243dSDimitry Andric bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order, 99bdd1243dSDimitry Andric SmallVectorImpl<MCPhysReg> &Hints, 100bdd1243dSDimitry Andric const MachineFunction &MF, const VirtRegMap *VRM, 101bdd1243dSDimitry Andric const LiveRegMatrix *Matrix) const override; 1020b57cec5SDimitry Andric }; 1030b57cec5SDimitry Andric } 1040b57cec5SDimitry Andric 1050b57cec5SDimitry Andric #endif 106