1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVRegisterInfo.h" 14 #include "RISCV.h" 15 #include "RISCVSubtarget.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/RegisterScavenging.h" 20 #include "llvm/CodeGen/TargetFrameLowering.h" 21 #include "llvm/CodeGen/TargetInstrInfo.h" 22 #include "llvm/Support/ErrorHandling.h" 23 24 #define GET_REGINFO_TARGET_DESC 25 #include "RISCVGenRegisterInfo.inc" 26 27 using namespace llvm; 28 29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive"); 30 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive"); 31 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive"); 32 static_assert(RISCV::F31_F == RISCV::F0_F + 31, 33 "Register list not consecutive"); 34 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive"); 35 static_assert(RISCV::F31_D == RISCV::F0_D + 31, 36 "Register list not consecutive"); 37 38 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) 39 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0, 40 /*PC*/0, HwMode) {} 41 42 const MCPhysReg * 43 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 44 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>(); 45 if (MF->getFunction().hasFnAttribute("interrupt")) { 46 if (Subtarget.hasStdExtD()) 47 return CSR_XLEN_F64_Interrupt_SaveList; 48 if (Subtarget.hasStdExtF()) 49 return CSR_XLEN_F32_Interrupt_SaveList; 50 return CSR_Interrupt_SaveList; 51 } 52 53 switch (Subtarget.getTargetABI()) { 54 default: 55 llvm_unreachable("Unrecognized ABI"); 56 case RISCVABI::ABI_ILP32: 57 case RISCVABI::ABI_LP64: 58 return CSR_ILP32_LP64_SaveList; 59 case RISCVABI::ABI_ILP32F: 60 case RISCVABI::ABI_LP64F: 61 return CSR_ILP32F_LP64F_SaveList; 62 case RISCVABI::ABI_ILP32D: 63 case RISCVABI::ABI_LP64D: 64 return CSR_ILP32D_LP64D_SaveList; 65 } 66 } 67 68 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 69 const TargetFrameLowering *TFI = getFrameLowering(MF); 70 BitVector Reserved(getNumRegs()); 71 72 // Use markSuperRegs to ensure any register aliases are also reserved 73 markSuperRegs(Reserved, RISCV::X0); // zero 74 markSuperRegs(Reserved, RISCV::X1); // ra 75 markSuperRegs(Reserved, RISCV::X2); // sp 76 markSuperRegs(Reserved, RISCV::X3); // gp 77 markSuperRegs(Reserved, RISCV::X4); // tp 78 if (TFI->hasFP(MF)) 79 markSuperRegs(Reserved, RISCV::X8); // fp 80 assert(checkAllSuperRegsMarked(Reserved)); 81 return Reserved; 82 } 83 84 bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const { 85 return PhysReg == RISCV::X0; 86 } 87 88 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { 89 return CSR_NoRegs_RegMask; 90 } 91 92 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 93 int SPAdj, unsigned FIOperandNum, 94 RegScavenger *RS) const { 95 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value"); 96 97 MachineInstr &MI = *II; 98 MachineFunction &MF = *MI.getParent()->getParent(); 99 MachineRegisterInfo &MRI = MF.getRegInfo(); 100 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); 101 DebugLoc DL = MI.getDebugLoc(); 102 103 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 104 unsigned FrameReg; 105 int Offset = 106 getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + 107 MI.getOperand(FIOperandNum + 1).getImm(); 108 109 if (!isInt<32>(Offset)) { 110 report_fatal_error( 111 "Frame offsets outside of the signed 32-bit range not supported"); 112 } 113 114 MachineBasicBlock &MBB = *MI.getParent(); 115 bool FrameRegIsKill = false; 116 117 if (!isInt<12>(Offset)) { 118 assert(isInt<32>(Offset) && "Int32 expected"); 119 // The offset won't fit in an immediate, so use a scratch register instead 120 // Modify Offset and FrameReg appropriately 121 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 122 TII->movImm(MBB, II, DL, ScratchReg, Offset); 123 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg) 124 .addReg(FrameReg) 125 .addReg(ScratchReg, RegState::Kill); 126 Offset = 0; 127 FrameReg = ScratchReg; 128 FrameRegIsKill = true; 129 } 130 131 MI.getOperand(FIOperandNum) 132 .ChangeToRegister(FrameReg, false, false, FrameRegIsKill); 133 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 134 } 135 136 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 137 const TargetFrameLowering *TFI = getFrameLowering(MF); 138 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2; 139 } 140 141 const uint32_t * 142 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF, 143 CallingConv::ID /*CC*/) const { 144 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); 145 if (MF.getFunction().hasFnAttribute("interrupt")) { 146 if (Subtarget.hasStdExtD()) 147 return CSR_XLEN_F64_Interrupt_RegMask; 148 if (Subtarget.hasStdExtF()) 149 return CSR_XLEN_F32_Interrupt_RegMask; 150 return CSR_Interrupt_RegMask; 151 } 152 153 switch (Subtarget.getTargetABI()) { 154 default: 155 llvm_unreachable("Unrecognized ABI"); 156 case RISCVABI::ABI_ILP32: 157 case RISCVABI::ABI_LP64: 158 return CSR_ILP32_LP64_RegMask; 159 case RISCVABI::ABI_ILP32F: 160 case RISCVABI::ABI_LP64F: 161 return CSR_ILP32F_LP64F_RegMask; 162 case RISCVABI::ABI_ILP32D: 163 case RISCVABI::ABI_LP64D: 164 return CSR_ILP32D_LP64D_RegMask; 165 } 166 } 167