1//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// RISC-V processors supported. 11//===----------------------------------------------------------------------===// 12 13class RISCVTuneInfo { 14 bits<8> PrefFunctionAlignment = 1; 15 bits<8> PrefLoopAlignment = 1; 16 17 // Information needed by LoopDataPrefetch. 18 bits<16> CacheLineSize = 0; 19 bits<16> PrefetchDistance = 0; 20 bits<16> MinPrefetchStride = 1; 21 bits<32> MaxPrefetchIterationsAhead = -1; 22 23 bits<32> MinimumJumpTableEntries = 5; 24} 25 26def RISCVTuneInfoTable : GenericTable { 27 let FilterClass = "RISCVTuneInfo"; 28 let CppTypeName = "RISCVTuneInfo"; 29 let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment", 30 "CacheLineSize", "PrefetchDistance", 31 "MinPrefetchStride", "MaxPrefetchIterationsAhead", 32 "MinimumJumpTableEntries"]; 33} 34 35def getRISCVTuneInfo : SearchIndex { 36 let Table = RISCVTuneInfoTable; 37 let Key = ["Name"]; 38} 39 40class GenericTuneInfo: RISCVTuneInfo; 41 42class RISCVProcessorModel<string n, 43 SchedMachineModel m, 44 list<SubtargetFeature> f, 45 list<SubtargetFeature> tunef = [], 46 string default_march = ""> 47 : ProcessorModel<n, m, f, tunef> { 48 string DefaultMarch = default_march; 49} 50 51class RISCVTuneProcessorModel<string n, 52 SchedMachineModel m, 53 list<SubtargetFeature> tunef = [], 54 list<SubtargetFeature> f = []> 55 : ProcessorModel<n, m, f,tunef>; 56 57def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32", 58 NoSchedModel, 59 [Feature32Bit, 60 FeatureStdExtI]>, 61 GenericTuneInfo; 62def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", 63 NoSchedModel, 64 [Feature64Bit, 65 FeatureStdExtI]>, 66 GenericTuneInfo; 67// Support generic for compatibility with other targets. The triple will be used 68// to change to the appropriate rv32/rv64 version. 69def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo; 70 71def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32", 72 RocketModel, 73 [Feature32Bit, 74 FeatureStdExtI, 75 FeatureStdExtZifencei, 76 FeatureStdExtZicsr]>; 77def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64", 78 RocketModel, 79 [Feature64Bit, 80 FeatureStdExtI, 81 FeatureStdExtZifencei, 82 FeatureStdExtZicsr]>; 83def ROCKET : RISCVTuneProcessorModel<"rocket", 84 RocketModel>; 85 86def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series", 87 SiFive7Model, 88 [TuneSiFive7, FeaturePostRAScheduler]>; 89 90def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20", 91 RocketModel, 92 [Feature32Bit, 93 FeatureStdExtI, 94 FeatureStdExtZicsr, 95 FeatureStdExtZifencei, 96 FeatureStdExtM, 97 FeatureStdExtC]>; 98 99def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21", 100 RocketModel, 101 [Feature32Bit, 102 FeatureStdExtI, 103 FeatureStdExtZicsr, 104 FeatureStdExtZifencei, 105 FeatureStdExtM, 106 FeatureStdExtA, 107 FeatureStdExtC]>; 108 109def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24", 110 RocketModel, 111 [Feature32Bit, 112 FeatureStdExtI, 113 FeatureStdExtZifencei, 114 FeatureStdExtM, 115 FeatureStdExtA, 116 FeatureStdExtF, 117 FeatureStdExtC]>; 118 119def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31", 120 RocketModel, 121 [Feature32Bit, 122 FeatureStdExtI, 123 FeatureStdExtZifencei, 124 FeatureStdExtZicsr, 125 FeatureStdExtM, 126 FeatureStdExtA, 127 FeatureStdExtC]>; 128 129def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34", 130 RocketModel, 131 [Feature32Bit, 132 FeatureStdExtI, 133 FeatureStdExtZifencei, 134 FeatureStdExtM, 135 FeatureStdExtA, 136 FeatureStdExtF, 137 FeatureStdExtC]>; 138 139def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76", 140 SiFive7Model, 141 [Feature32Bit, 142 FeatureStdExtI, 143 FeatureStdExtZifencei, 144 FeatureStdExtM, 145 FeatureStdExtA, 146 FeatureStdExtF, 147 FeatureStdExtC], 148 [TuneSiFive7, FeaturePostRAScheduler]>; 149 150def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21", 151 RocketModel, 152 [Feature64Bit, 153 FeatureStdExtI, 154 FeatureStdExtZicsr, 155 FeatureStdExtZifencei, 156 FeatureStdExtM, 157 FeatureStdExtA, 158 FeatureStdExtC]>; 159 160def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51", 161 RocketModel, 162 [Feature64Bit, 163 FeatureStdExtI, 164 FeatureStdExtZicsr, 165 FeatureStdExtZifencei, 166 FeatureStdExtM, 167 FeatureStdExtA, 168 FeatureStdExtC]>; 169 170def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54", 171 RocketModel, 172 [Feature64Bit, 173 FeatureStdExtI, 174 FeatureStdExtZifencei, 175 FeatureStdExtM, 176 FeatureStdExtA, 177 FeatureStdExtF, 178 FeatureStdExtD, 179 FeatureStdExtC]>; 180 181def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76", 182 SiFive7Model, 183 [Feature64Bit, 184 FeatureStdExtI, 185 FeatureStdExtZifencei, 186 FeatureStdExtM, 187 FeatureStdExtA, 188 FeatureStdExtF, 189 FeatureStdExtD, 190 FeatureStdExtC, 191 FeatureStdExtZihintpause], 192 [TuneSiFive7, FeaturePostRAScheduler]>; 193 194def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54", 195 RocketModel, 196 [Feature64Bit, 197 FeatureStdExtI, 198 FeatureStdExtZifencei, 199 FeatureStdExtM, 200 FeatureStdExtA, 201 FeatureStdExtF, 202 FeatureStdExtD, 203 FeatureStdExtC]>; 204 205def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74", 206 SiFive7Model, 207 [Feature64Bit, 208 FeatureStdExtI, 209 FeatureStdExtZifencei, 210 FeatureStdExtM, 211 FeatureStdExtA, 212 FeatureStdExtF, 213 FeatureStdExtD, 214 FeatureStdExtC], 215 [TuneSiFive7, FeaturePostRAScheduler]>; 216 217def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, 218 [Feature64Bit, 219 FeatureStdExtI, 220 FeatureStdExtZifencei, 221 FeatureStdExtM, 222 FeatureStdExtA, 223 FeatureStdExtF, 224 FeatureStdExtD, 225 FeatureStdExtC, 226 FeatureStdExtV, 227 FeatureStdExtZvl512b, 228 FeatureStdExtZfh, 229 FeatureStdExtZvfh, 230 FeatureStdExtZba, 231 FeatureStdExtZbb], 232 [TuneSiFive7, 233 FeaturePostRAScheduler, 234 TuneDLenFactor2, 235 TuneOptimizedZeroStrideLoad]>; 236 237def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, 238 [Feature64Bit, 239 FeatureStdExtI, 240 FeatureStdExtZifencei, 241 FeatureStdExtM, 242 FeatureStdExtA, 243 FeatureStdExtF, 244 FeatureStdExtD, 245 FeatureStdExtC, 246 FeatureStdExtZa64rs, 247 FeatureStdExtZic64b, 248 FeatureStdExtZicbop, 249 FeatureStdExtZicbom, 250 FeatureStdExtZicboz, 251 FeatureStdExtZiccamoa, 252 FeatureStdExtZiccif, 253 FeatureStdExtZicclsm, 254 FeatureStdExtZiccrse, 255 FeatureStdExtZihintntl, 256 FeatureStdExtZihintpause, 257 FeatureStdExtZihpm, 258 FeatureStdExtZba, 259 FeatureStdExtZbb, 260 FeatureStdExtZbs, 261 FeatureStdExtZfhmin, 262 FeatureUnalignedScalarMem, 263 FeatureUnalignedVectorMem], 264 [TuneNoDefaultUnroll, 265 TuneConditionalCompressedMoveFusion, 266 TuneLUIADDIFusion, 267 TuneAUIPCADDIFusion, 268 FeaturePostRAScheduler]>; 269 270def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, 271 [Feature64Bit, 272 FeatureStdExtI, 273 FeatureStdExtZifencei, 274 FeatureStdExtM, 275 FeatureStdExtA, 276 FeatureStdExtF, 277 FeatureStdExtD, 278 FeatureStdExtC, 279 FeatureStdExtZa64rs, 280 FeatureStdExtZic64b, 281 FeatureStdExtZicbop, 282 FeatureStdExtZicbom, 283 FeatureStdExtZicboz, 284 FeatureStdExtZiccamoa, 285 FeatureStdExtZiccif, 286 FeatureStdExtZicclsm, 287 FeatureStdExtZiccrse, 288 FeatureStdExtZihintntl, 289 FeatureStdExtZihintpause, 290 FeatureStdExtZihpm, 291 FeatureStdExtZba, 292 FeatureStdExtZbb, 293 FeatureStdExtZbs, 294 FeatureStdExtZfhmin, 295 FeatureStdExtV, 296 FeatureStdExtZvl128b, 297 FeatureStdExtZvbb, 298 FeatureStdExtZvknc, 299 FeatureStdExtZvkng, 300 FeatureStdExtZvksc, 301 FeatureStdExtZvksg, 302 FeatureUnalignedScalarMem, 303 FeatureUnalignedVectorMem], 304 [TuneNoDefaultUnroll, 305 TuneConditionalCompressedMoveFusion, 306 TuneLUIADDIFusion, 307 TuneAUIPCADDIFusion, 308 TuneNoSinkSplatOperands, 309 FeaturePostRAScheduler]>; 310 311def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", 312 SyntacoreSCR1Model, 313 [Feature32Bit, 314 FeatureStdExtI, 315 FeatureStdExtZicsr, 316 FeatureStdExtZifencei, 317 FeatureStdExtC], 318 [TuneNoDefaultUnroll]>; 319 320def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", 321 SyntacoreSCR1Model, 322 [Feature32Bit, 323 FeatureStdExtI, 324 FeatureStdExtZicsr, 325 FeatureStdExtZifencei, 326 FeatureStdExtM, 327 FeatureStdExtC], 328 [TuneNoDefaultUnroll]>; 329 330def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32", 331 SyntacoreSCR3RV32Model, 332 [Feature32Bit, 333 FeatureStdExtI, 334 FeatureStdExtZicsr, 335 FeatureStdExtZifencei, 336 FeatureStdExtM, 337 FeatureStdExtC], 338 [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; 339 340def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", 341 SyntacoreSCR3RV64Model, 342 [Feature64Bit, 343 FeatureStdExtI, 344 FeatureStdExtZicsr, 345 FeatureStdExtZifencei, 346 FeatureStdExtM, 347 FeatureStdExtA, 348 FeatureStdExtC], 349 [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; 350 351def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", 352 NoSchedModel, 353 [Feature64Bit, 354 FeatureStdExtI, 355 FeatureStdExtZifencei, 356 FeatureStdExtZicsr, 357 FeatureStdExtZicntr, 358 FeatureStdExtZihpm, 359 FeatureStdExtZihintpause, 360 FeatureStdExtM, 361 FeatureStdExtA, 362 FeatureStdExtF, 363 FeatureStdExtD, 364 FeatureStdExtC, 365 FeatureStdExtZba, 366 FeatureStdExtZbb, 367 FeatureStdExtZbc, 368 FeatureStdExtZbs, 369 FeatureStdExtZicbom, 370 FeatureStdExtZicbop, 371 FeatureStdExtZicboz, 372 FeatureVendorXVentanaCondOps], 373 [TuneVentanaVeyron, 374 TuneLUIADDIFusion, 375 TuneAUIPCADDIFusion, 376 TuneZExtHFusion, 377 TuneZExtWFusion, 378 TuneShiftedZExtWFusion, 379 TuneLDADDFusion]>; 380 381def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", 382 XiangShanNanHuModel, 383 [Feature64Bit, 384 FeatureStdExtI, 385 FeatureStdExtZicsr, 386 FeatureStdExtZifencei, 387 FeatureStdExtM, 388 FeatureStdExtA, 389 FeatureStdExtF, 390 FeatureStdExtD, 391 FeatureStdExtC, 392 FeatureStdExtZba, 393 FeatureStdExtZbb, 394 FeatureStdExtZbc, 395 FeatureStdExtZbs, 396 FeatureStdExtZkn, 397 FeatureStdExtZksed, 398 FeatureStdExtZksh, 399 FeatureStdExtSvinval, 400 FeatureStdExtZicbom, 401 FeatureStdExtZicboz], 402 [TuneNoDefaultUnroll, 403 TuneZExtHFusion, 404 TuneZExtWFusion, 405 TuneShiftedZExtWFusion]>; 406 407def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", 408 NoSchedModel, 409 !listconcat(RVA22S64Features, 410 [FeatureStdExtV, 411 FeatureStdExtSscofpmf, 412 FeatureStdExtSstc, 413 FeatureStdExtSvnapot, 414 FeatureStdExtZbc, 415 FeatureStdExtZbkc, 416 FeatureStdExtZfh, 417 FeatureStdExtZicond, 418 FeatureStdExtZvfh, 419 FeatureStdExtZvkt, 420 FeatureStdExtZvl256b]), 421 [TuneDLenFactor2]>; 422