xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVProcessors.td (revision 7ef62cebc2f965b0f640263e179276928885e33d) 
1//===-- RISCVProcessors.td - RISCV Processors --------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// RISC-V processors supported.
11//===----------------------------------------------------------------------===//
12
13class RISCVProcessorModel<string n,
14                          SchedMachineModel m,
15                          list<SubtargetFeature> f,
16                          list<SubtargetFeature> tunef = [],
17                          string default_march = "">
18      :  ProcessorModel<n, m, f, tunef> {
19  string DefaultMarch = default_march;
20}
21
22class RISCVTuneProcessorModel<string n,
23                              SchedMachineModel m,
24                              list<SubtargetFeature> tunef = [],
25                              list<SubtargetFeature> f = []>
26      : ProcessorModel<n, m, f,tunef>;
27
28def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
29                                       NoSchedModel,
30                                       [Feature32Bit]>;
31def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
32                                       NoSchedModel,
33                                       [Feature64Bit]>;
34// Support generic for compatibility with other targets. The triple will be used
35// to change to the appropriate rv32/rv64 version.
36def : ProcessorModel<"generic", NoSchedModel, []>;
37
38def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
39                                      RocketModel,
40                                      [Feature32Bit]>;
41def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
42                                      RocketModel,
43                                      [Feature64Bit]>;
44def ROCKET : RISCVTuneProcessorModel<"rocket",
45                                     RocketModel>;
46
47def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
48                                       SiFive7Model,
49                                       [TuneSiFive7]>;
50
51def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
52                                     RocketModel,
53                                     [Feature32Bit,
54                                      FeatureStdExtM,
55                                      FeatureStdExtC]>;
56
57def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
58                                     RocketModel,
59                                     [Feature32Bit,
60                                      FeatureStdExtM,
61                                      FeatureStdExtA,
62                                      FeatureStdExtC]>;
63
64def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
65                                     RocketModel,
66                                     [Feature32Bit,
67                                      FeatureStdExtM,
68                                      FeatureStdExtA,
69                                      FeatureStdExtF,
70                                      FeatureStdExtC]>;
71
72def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
73                                     RocketModel,
74                                     [Feature32Bit,
75                                      FeatureStdExtM,
76                                      FeatureStdExtA,
77                                      FeatureStdExtC]>;
78
79def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
80                                     RocketModel,
81                                     [Feature32Bit,
82                                      FeatureStdExtM,
83                                      FeatureStdExtA,
84                                      FeatureStdExtF,
85                                      FeatureStdExtC]>;
86
87def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
88                                     SiFive7Model,
89                                     [Feature32Bit,
90                                      FeatureStdExtM,
91                                      FeatureStdExtA,
92                                      FeatureStdExtF,
93                                      FeatureStdExtC],
94                                     [TuneSiFive7]>;
95
96def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
97                                     RocketModel,
98                                     [Feature64Bit,
99                                      FeatureStdExtM,
100                                      FeatureStdExtA,
101                                      FeatureStdExtC]>;
102
103def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
104                                     RocketModel,
105                                     [Feature64Bit,
106                                      FeatureStdExtM,
107                                      FeatureStdExtA,
108                                      FeatureStdExtC]>;
109
110def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
111                                      RocketModel,
112                                      [Feature64Bit,
113                                       FeatureStdExtM,
114                                       FeatureStdExtA,
115                                       FeatureStdExtF,
116                                       FeatureStdExtD,
117                                       FeatureStdExtC]>;
118
119def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
120                                     SiFive7Model,
121                                     [Feature64Bit,
122                                      FeatureStdExtM,
123                                      FeatureStdExtA,
124                                      FeatureStdExtF,
125                                      FeatureStdExtD,
126                                      FeatureStdExtC],
127                                     [TuneSiFive7]>;
128
129def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
130                                     RocketModel,
131                                     [Feature64Bit,
132                                      FeatureStdExtM,
133                                      FeatureStdExtA,
134                                      FeatureStdExtF,
135                                      FeatureStdExtD,
136                                      FeatureStdExtC]>;
137
138def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
139                                     SiFive7Model,
140                                     [Feature64Bit,
141                                      FeatureStdExtM,
142                                      FeatureStdExtA,
143                                      FeatureStdExtF,
144                                      FeatureStdExtD,
145                                      FeatureStdExtC],
146                                     [TuneSiFive7]>;
147
148def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
149                                              SyntacoreSCR1Model,
150                                              [Feature32Bit,
151                                               FeatureStdExtC],
152                                              [TuneNoDefaultUnroll]>;
153
154def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
155                                             SyntacoreSCR1Model,
156                                             [Feature32Bit,
157                                              FeatureStdExtM,
158                                              FeatureStdExtC],
159                                             [TuneNoDefaultUnroll]>;
160