xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVProcessors.td (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// RISC-V processors supported.
11//===----------------------------------------------------------------------===//
12
13class RISCVProcessorModel<string n,
14                          SchedMachineModel m,
15                          list<SubtargetFeature> f,
16                          list<SubtargetFeature> tunef = [],
17                          string default_march = "">
18      :  ProcessorModel<n, m, f, tunef> {
19  string DefaultMarch = default_march;
20}
21
22class RISCVTuneProcessorModel<string n,
23                              SchedMachineModel m,
24                              list<SubtargetFeature> tunef = [],
25                              list<SubtargetFeature> f = []>
26      : ProcessorModel<n, m, f,tunef>;
27
28def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
29                                       NoSchedModel,
30                                       [Feature32Bit]>;
31def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
32                                       NoSchedModel,
33                                       [Feature64Bit]>;
34// Support generic for compatibility with other targets. The triple will be used
35// to change to the appropriate rv32/rv64 version.
36def : ProcessorModel<"generic", NoSchedModel, []>;
37
38def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
39                                      RocketModel,
40                                      [Feature32Bit,
41                                       FeatureStdExtZifencei,
42                                       FeatureStdExtZicsr]>;
43def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
44                                      RocketModel,
45                                      [Feature64Bit,
46                                       FeatureStdExtZifencei,
47                                       FeatureStdExtZicsr]>;
48def ROCKET : RISCVTuneProcessorModel<"rocket",
49                                     RocketModel>;
50
51def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
52                                       SiFive7Model,
53                                       [TuneSiFive7]>;
54
55def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
56                                     RocketModel,
57                                     [Feature32Bit,
58                                      FeatureStdExtZicsr,
59                                      FeatureStdExtZifencei,
60                                      FeatureStdExtM,
61                                      FeatureStdExtC]>;
62
63def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
64                                     RocketModel,
65                                     [Feature32Bit,
66                                      FeatureStdExtZicsr,
67                                      FeatureStdExtZifencei,
68                                      FeatureStdExtM,
69                                      FeatureStdExtA,
70                                      FeatureStdExtC]>;
71
72def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
73                                     RocketModel,
74                                     [Feature32Bit,
75                                      FeatureStdExtZifencei,
76                                      FeatureStdExtM,
77                                      FeatureStdExtA,
78                                      FeatureStdExtF,
79                                      FeatureStdExtC]>;
80
81def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
82                                     RocketModel,
83                                     [Feature32Bit,
84                                      FeatureStdExtZifencei,
85                                      FeatureStdExtZicsr,
86                                      FeatureStdExtM,
87                                      FeatureStdExtA,
88                                      FeatureStdExtC]>;
89
90def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
91                                     RocketModel,
92                                     [Feature32Bit,
93                                      FeatureStdExtZifencei,
94                                      FeatureStdExtM,
95                                      FeatureStdExtA,
96                                      FeatureStdExtF,
97                                      FeatureStdExtC]>;
98
99def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
100                                     SiFive7Model,
101                                     [Feature32Bit,
102                                      FeatureStdExtZifencei,
103                                      FeatureStdExtM,
104                                      FeatureStdExtA,
105                                      FeatureStdExtF,
106                                      FeatureStdExtC],
107                                     [TuneSiFive7]>;
108
109def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
110                                     RocketModel,
111                                     [Feature64Bit,
112                                      FeatureStdExtZicsr,
113                                      FeatureStdExtZifencei,
114                                      FeatureStdExtM,
115                                      FeatureStdExtA,
116                                      FeatureStdExtC]>;
117
118def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
119                                     RocketModel,
120                                     [Feature64Bit,
121                                      FeatureStdExtZicsr,
122                                      FeatureStdExtZifencei,
123                                      FeatureStdExtM,
124                                      FeatureStdExtA,
125                                      FeatureStdExtC]>;
126
127def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
128                                      RocketModel,
129                                      [Feature64Bit,
130                                       FeatureStdExtZifencei,
131                                       FeatureStdExtM,
132                                       FeatureStdExtA,
133                                       FeatureStdExtF,
134                                       FeatureStdExtD,
135                                       FeatureStdExtC]>;
136
137def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
138                                     SiFive7Model,
139                                     [Feature64Bit,
140                                      FeatureStdExtZifencei,
141                                      FeatureStdExtM,
142                                      FeatureStdExtA,
143                                      FeatureStdExtF,
144                                      FeatureStdExtD,
145                                      FeatureStdExtC,
146                                      FeatureStdExtZihintpause,
147                                      FeatureVendorXSfcie],
148                                     [TuneSiFive7]>;
149
150def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
151                                     RocketModel,
152                                     [Feature64Bit,
153                                      FeatureStdExtZifencei,
154                                      FeatureStdExtM,
155                                      FeatureStdExtA,
156                                      FeatureStdExtF,
157                                      FeatureStdExtD,
158                                      FeatureStdExtC]>;
159
160def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
161                                     SiFive7Model,
162                                     [Feature64Bit,
163                                      FeatureStdExtZifencei,
164                                      FeatureStdExtM,
165                                      FeatureStdExtA,
166                                      FeatureStdExtF,
167                                      FeatureStdExtD,
168                                      FeatureStdExtC],
169                                     [TuneSiFive7]>;
170
171def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
172                                      [Feature64Bit,
173                                       FeatureStdExtZifencei,
174                                       FeatureStdExtM,
175                                       FeatureStdExtA,
176                                       FeatureStdExtF,
177                                       FeatureStdExtD,
178                                       FeatureStdExtC,
179                                       FeatureStdExtV,
180                                       FeatureStdExtZvl512b,
181                                       FeatureStdExtZfh,
182                                       FeatureStdExtZvfh,
183                                       FeatureStdExtZba,
184                                       FeatureStdExtZbb],
185                                      [TuneSiFive7,
186                                       TuneDLenFactor2]>;
187
188def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
189                                              SyntacoreSCR1Model,
190                                              [Feature32Bit,
191                                               FeatureStdExtZicsr,
192                                               FeatureStdExtZifencei,
193                                               FeatureStdExtC],
194                                              [TuneNoDefaultUnroll]>;
195
196def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
197                                             SyntacoreSCR1Model,
198                                             [Feature32Bit,
199                                              FeatureStdExtZicsr,
200                                              FeatureStdExtZifencei,
201                                              FeatureStdExtM,
202                                              FeatureStdExtC],
203                                             [TuneNoDefaultUnroll]>;
204