1 //===-- RISCVPostRAExpandPseudoInsts.cpp - Expand pseudo instrs ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains a pass that expands the pseudo instruction pseudolisimm32 10 // into target instructions. This pass should be run during the post-regalloc 11 // passes, before post RA scheduling. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MCTargetDesc/RISCVMatInt.h" 16 #include "RISCV.h" 17 #include "RISCVInstrInfo.h" 18 #include "RISCVTargetMachine.h" 19 #include "llvm/CodeGen/MachineFunctionPass.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 22 using namespace llvm; 23 24 #define RISCV_POST_RA_EXPAND_PSEUDO_NAME \ 25 "RISC-V post-regalloc pseudo instruction expansion pass" 26 27 namespace { 28 29 class RISCVPostRAExpandPseudo : public MachineFunctionPass { 30 public: 31 const RISCVInstrInfo *TII; 32 static char ID; 33 34 RISCVPostRAExpandPseudo() : MachineFunctionPass(ID) {} 35 36 bool runOnMachineFunction(MachineFunction &MF) override; 37 38 StringRef getPassName() const override { 39 return RISCV_POST_RA_EXPAND_PSEUDO_NAME; 40 } 41 42 private: 43 bool expandMBB(MachineBasicBlock &MBB); 44 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 45 MachineBasicBlock::iterator &NextMBBI); 46 bool expandMovImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI); 47 bool expandMovAddr(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI); 48 }; 49 50 char RISCVPostRAExpandPseudo::ID = 0; 51 52 bool RISCVPostRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 53 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo()); 54 bool Modified = false; 55 for (auto &MBB : MF) 56 Modified |= expandMBB(MBB); 57 return Modified; 58 } 59 60 bool RISCVPostRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) { 61 bool Modified = false; 62 63 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 64 while (MBBI != E) { 65 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 66 Modified |= expandMI(MBB, MBBI, NMBBI); 67 MBBI = NMBBI; 68 } 69 70 return Modified; 71 } 72 73 bool RISCVPostRAExpandPseudo::expandMI(MachineBasicBlock &MBB, 74 MachineBasicBlock::iterator MBBI, 75 MachineBasicBlock::iterator &NextMBBI) { 76 switch (MBBI->getOpcode()) { 77 case RISCV::PseudoMovImm: 78 return expandMovImm(MBB, MBBI); 79 case RISCV::PseudoMovAddr: 80 return expandMovAddr(MBB, MBBI); 81 default: 82 return false; 83 } 84 } 85 86 bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator MBBI) { 88 DebugLoc DL = MBBI->getDebugLoc(); 89 90 int64_t Val = MBBI->getOperand(1).getImm(); 91 92 Register DstReg = MBBI->getOperand(0).getReg(); 93 bool DstIsDead = MBBI->getOperand(0).isDead(); 94 bool Renamable = MBBI->getOperand(0).isRenamable(); 95 96 TII->movImm(MBB, MBBI, DL, DstReg, Val, MachineInstr::NoFlags, Renamable, 97 DstIsDead); 98 99 MBBI->eraseFromParent(); 100 return true; 101 } 102 103 bool RISCVPostRAExpandPseudo::expandMovAddr(MachineBasicBlock &MBB, 104 MachineBasicBlock::iterator MBBI) { 105 DebugLoc DL = MBBI->getDebugLoc(); 106 107 Register DstReg = MBBI->getOperand(0).getReg(); 108 bool DstIsDead = MBBI->getOperand(0).isDead(); 109 bool Renamable = MBBI->getOperand(0).isRenamable(); 110 111 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LUI)) 112 .addReg(DstReg, RegState::Define | getRenamableRegState(Renamable)) 113 .add(MBBI->getOperand(1)); 114 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI)) 115 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead) | 116 getRenamableRegState(Renamable)) 117 .addReg(DstReg, RegState::Kill | getRenamableRegState(Renamable)) 118 .add(MBBI->getOperand(2)); 119 MBBI->eraseFromParent(); 120 return true; 121 } 122 123 } // end of anonymous namespace 124 125 INITIALIZE_PASS(RISCVPostRAExpandPseudo, "riscv-expand-pseudolisimm32", 126 RISCV_POST_RA_EXPAND_PSEUDO_NAME, false, false) 127 namespace llvm { 128 129 FunctionPass *createRISCVPostRAExpandPseudoPass() { 130 return new RISCVPostRAExpandPseudo(); 131 } 132 133 } // end of namespace llvm 134