xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td (revision 1db9f3b21e39176dd5b67cf8ac378633b172463e)
1//===-- RISCVInstrInfoZimop.td -----------------------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the RISC-V instructions from the standard
10// May-Be-Operations Extension (Zimop).
11// This version is still experimental as the 'Zimop' extension hasn't been
12// ratified yet. It is based on v0.1 of the specification.
13//
14//===----------------------------------------------------------------------===//
15
16class RVInstIMopr<bits<7> imm7, bits<5> imm5, bits<3> funct3, RISCVOpcode opcode,
17                   dag outs, dag ins, string opcodestr, string argstr>
18    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
19  let Inst{31} = imm7{6};
20  let Inst{30} = imm5{4};
21  let Inst{29-28} = imm7{5-4};
22  let Inst{27-26} = imm5{3-2};
23  let Inst{25-22} = imm7{3-0};
24  let Inst{21-20} = imm5{1-0};
25}
26
27class RVInstRMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3, RISCVOpcode opcode,
28                   dag outs, dag ins, string opcodestr, string argstr>
29    : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
30  let Inst{31} = imm4{3};
31  let Inst{30} = imm3{2};
32  let Inst{29-28} = imm4{2-1};
33  let Inst{27-26} = imm3{1-0};
34  let Inst{25} = imm4{0};
35}
36
37let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
38class RVMopr<bits<7> imm7, bits<5> imm5, bits<3> funct3,
39             RISCVOpcode opcode, string opcodestr>
40    : RVInstIMopr<imm7, imm5, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
41                   opcodestr, "$rd, $rs1">;
42
43let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
44class RVMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3,
45             RISCVOpcode opcode, string opcodestr>
46    : RVInstRMoprr<imm4, imm3, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
47                   opcodestr, "$rd, $rs1, $rs2">;
48
49foreach i = 0...31 in {
50  let Predicates = [HasStdExtZimop] in
51  def MOPR#i : RVMopr<0b1000111, i, 0b100, OPC_SYSTEM, "mop.r."#i>,
52               Sched<[]>;
53}
54
55foreach i = 0...7 in {
56  let Predicates = [HasStdExtZimop] in
57  def MOPRR#i : RVMoprr<0b1001, i, 0b100, OPC_SYSTEM, "mop.rr."#i>,
58                Sched<[]>;
59}
60