1*700637cbSDimitry Andric//===-- RISCVInstrInfoZilsd.td -----------------------------*- tablegen -*-===// 2*700637cbSDimitry Andric// 3*700637cbSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*700637cbSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*700637cbSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*700637cbSDimitry Andric// 7*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 8*700637cbSDimitry Andric// 9*700637cbSDimitry Andric// This file describes the RISC-V instructions from the standard 'Zilsd', 10*700637cbSDimitry Andric// Load/Store pair instructions extension. 11*700637cbSDimitry Andric// 12*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 13*700637cbSDimitry Andric 14*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 15*700637cbSDimitry Andric// RISC-V specific DAG Nodes. 16*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 17*700637cbSDimitry Andric 18*700637cbSDimitry Andricdef SDT_RISCV_LD_RV32 19*700637cbSDimitry Andric : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<2>]>; 20*700637cbSDimitry Andricdef SDT_RISCV_SD_RV32 21*700637cbSDimitry Andric : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<2>]>; 22*700637cbSDimitry Andric 23*700637cbSDimitry Andricdef riscv_ld_rv32 : RVSDNode<"LD_RV32", SDT_RISCV_LD_RV32, 24*700637cbSDimitry Andric [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 25*700637cbSDimitry Andricdef riscv_st_rv32 : RVSDNode<"SD_RV32", SDT_RISCV_SD_RV32, 26*700637cbSDimitry Andric [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 27*700637cbSDimitry Andric 28*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 29*700637cbSDimitry Andric// Instruction Class Templates 30*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 31*700637cbSDimitry Andric 32*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 33*700637cbSDimitry Andric// Instructions 34*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 35*700637cbSDimitry Andric 36*700637cbSDimitry Andriclet Predicates = [HasStdExtZilsd, IsRV32], DecoderNamespace = "RV32Only" in { 37*700637cbSDimitry Andricdef LD_RV32 : Load_ri<0b011, "ld", GPRPairRV32>, Sched<[WriteLDD, ReadMemBase]>; 38*700637cbSDimitry Andricdef SD_RV32 : Store_rri<0b011, "sd", GPRPairRV32>, 39*700637cbSDimitry Andric Sched<[WriteSTD, ReadStoreData, ReadMemBase]>; 40*700637cbSDimitry Andric} // Predicates = [HasStdExtZilsd, IsRV32], DecoderNamespace = "RV32Only" 41*700637cbSDimitry Andric 42*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 43*700637cbSDimitry Andric// Assembler Pseudo Instructions 44*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 45*700637cbSDimitry Andric 46*700637cbSDimitry Andriclet Predicates = [HasStdExtZilsd, IsRV32] in { 47*700637cbSDimitry Andricdef PseudoLD_RV32 : PseudoLoad<"ld", GPRPairRV32>; 48*700637cbSDimitry Andricdef PseudoSD_RV32 : PseudoStore<"sd", GPRPairRV32>; 49*700637cbSDimitry Andric 50*700637cbSDimitry Andricdef : InstAlias<"ld $rd, (${rs1})", (LD_RV32 GPRPairRV32:$rd, GPR:$rs1, 0), 0>; 51*700637cbSDimitry Andricdef : InstAlias<"sd $rs2, (${rs1})", (SD_RV32 GPRPairRV32:$rs2, GPR:$rs1, 0), 0>; 52*700637cbSDimitry Andric} 53