106c3fb27SDimitry Andric//===-- RISCVInstrInfoZicond.td ----------------------------*- tablegen -*-===// 206c3fb27SDimitry Andric// 306c3fb27SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 406c3fb27SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 506c3fb27SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 606c3fb27SDimitry Andric// 706c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 806c3fb27SDimitry Andric// 906c3fb27SDimitry Andric// This file describes the RISC-V instructions from the standard Integer 1006c3fb27SDimitry Andric// Conditional operations extension (Zicond). 1106c3fb27SDimitry Andric// This version is still experimental as the 'Zicond' extension hasn't been 1206c3fb27SDimitry Andric// ratified yet. It is based on v1.0-rc1 of the specification. 1306c3fb27SDimitry Andric// 1406c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 1506c3fb27SDimitry Andric 1606c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 1706c3fb27SDimitry Andric// RISC-V specific DAG Nodes. 1806c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 1906c3fb27SDimitry Andric 2006c3fb27SDimitry Andricdef riscv_czero_eqz : SDNode<"RISCVISD::CZERO_EQZ", SDTIntBinOp>; 2106c3fb27SDimitry Andricdef riscv_czero_nez : SDNode<"RISCVISD::CZERO_NEZ", SDTIntBinOp>; 2206c3fb27SDimitry Andric 2306c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 2406c3fb27SDimitry Andric// Instructions 2506c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 2606c3fb27SDimitry Andric 2706c3fb27SDimitry Andriclet Predicates = [HasStdExtZicond] in { 2806c3fb27SDimitry Andricdef CZERO_EQZ : ALU_rr<0b0000111, 0b101, "czero.eqz">, 2906c3fb27SDimitry Andric Sched<[WriteIALU, ReadIALU, ReadIALU]>; 3006c3fb27SDimitry Andricdef CZERO_NEZ : ALU_rr<0b0000111, 0b111, "czero.nez">, 3106c3fb27SDimitry Andric Sched<[WriteIALU, ReadIALU, ReadIALU]>; 3206c3fb27SDimitry Andric} // Predicates = [HasStdExtZicond] 3306c3fb27SDimitry Andric 3406c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 3506c3fb27SDimitry Andric// Pseudo-instructions and codegen patterns 3606c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 3706c3fb27SDimitry Andric 3806c3fb27SDimitry Andriclet Predicates = [HasStdExtZicond] in { 3906c3fb27SDimitry Andricdef : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)), 4006c3fb27SDimitry Andric (CZERO_EQZ GPR:$rs1, GPR:$rc)>; 4106c3fb27SDimitry Andricdef : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)), 4206c3fb27SDimitry Andric (CZERO_NEZ GPR:$rs1, GPR:$rc)>; 43*5f757f3fSDimitry Andric 44*5f757f3fSDimitry Andricdef : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))), 45*5f757f3fSDimitry Andric (CZERO_EQZ GPR:$rs1, GPR:$rc)>; 46*5f757f3fSDimitry Andricdef : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))), 47*5f757f3fSDimitry Andric (CZERO_NEZ GPR:$rs1, GPR:$rc)>; 48*5f757f3fSDimitry Andricdef : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))), 49*5f757f3fSDimitry Andric (CZERO_NEZ GPR:$rs1, GPR:$rc)>; 50*5f757f3fSDimitry Andricdef : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))), 51*5f757f3fSDimitry Andric (CZERO_EQZ GPR:$rs1, GPR:$rc)>; 5206c3fb27SDimitry Andric} // Predicates = [HasStdExtZicond] 53