1*06c3fb27SDimitry Andric//===-- RISCVInstrInfoZicond.td ----------------------------*- tablegen -*-===// 2*06c3fb27SDimitry Andric// 3*06c3fb27SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*06c3fb27SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*06c3fb27SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*06c3fb27SDimitry Andric// 7*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 8*06c3fb27SDimitry Andric// 9*06c3fb27SDimitry Andric// This file describes the RISC-V instructions from the standard Integer 10*06c3fb27SDimitry Andric// Conditional operations extension (Zicond). 11*06c3fb27SDimitry Andric// This version is still experimental as the 'Zicond' extension hasn't been 12*06c3fb27SDimitry Andric// ratified yet. It is based on v1.0-rc1 of the specification. 13*06c3fb27SDimitry Andric// 14*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 15*06c3fb27SDimitry Andric 16*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 17*06c3fb27SDimitry Andric// RISC-V specific DAG Nodes. 18*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 19*06c3fb27SDimitry Andric 20*06c3fb27SDimitry Andricdef riscv_czero_eqz : SDNode<"RISCVISD::CZERO_EQZ", SDTIntBinOp>; 21*06c3fb27SDimitry Andricdef riscv_czero_nez : SDNode<"RISCVISD::CZERO_NEZ", SDTIntBinOp>; 22*06c3fb27SDimitry Andric 23*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 24*06c3fb27SDimitry Andric// Instructions 25*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 26*06c3fb27SDimitry Andric 27*06c3fb27SDimitry Andriclet Predicates = [HasStdExtZicond] in { 28*06c3fb27SDimitry Andricdef CZERO_EQZ : ALU_rr<0b0000111, 0b101, "czero.eqz">, 29*06c3fb27SDimitry Andric Sched<[WriteIALU, ReadIALU, ReadIALU]>; 30*06c3fb27SDimitry Andricdef CZERO_NEZ : ALU_rr<0b0000111, 0b111, "czero.nez">, 31*06c3fb27SDimitry Andric Sched<[WriteIALU, ReadIALU, ReadIALU]>; 32*06c3fb27SDimitry Andric} // Predicates = [HasStdExtZicond] 33*06c3fb27SDimitry Andric 34*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 35*06c3fb27SDimitry Andric// Pseudo-instructions and codegen patterns 36*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 37*06c3fb27SDimitry Andric 38*06c3fb27SDimitry Andriclet Predicates = [HasStdExtZicond] in { 39*06c3fb27SDimitry Andricdef : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)), 40*06c3fb27SDimitry Andric (CZERO_EQZ GPR:$rs1, GPR:$rc)>; 41*06c3fb27SDimitry Andricdef : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)), 42*06c3fb27SDimitry Andric (CZERO_NEZ GPR:$rs1, GPR:$rc)>; 43*06c3fb27SDimitry Andric} // Predicates = [HasStdExtZicond] 44