1//===-- RISCVInstrInfoZfh.td - RISC-V 'Zfh' instructions ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'Zfh' 10// half-precision floating-point extension, version 1.0. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVFMV_H_X 19 : SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>; 20def SDT_RISCVFMV_X_EXTH 21 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>; 22 23def riscv_fmv_h_x 24 : SDNode<"RISCVISD::FMV_H_X", SDT_RISCVFMV_H_X>; 25def riscv_fmv_x_anyexth 26 : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_EXTH>; 27def riscv_fmv_x_signexth 28 : SDNode<"RISCVISD::FMV_X_SIGNEXTH", SDT_RISCVFMV_X_EXTH>; 29 30//===----------------------------------------------------------------------===// 31// Operand and SDNode transformation definitions. 32//===----------------------------------------------------------------------===// 33 34// Zhinxmin and Zhinx 35 36def FPR16INX : RegisterOperand<GPRF16> { 37 let ParserMatchClass = GPRAsFPR; 38 let DecoderMethod = "DecodeGPRRegisterClass"; 39} 40 41def ZfhExt : ExtInfo<0, [HasStdExtZfh]>; 42def Zfh64Ext : ExtInfo<0, [HasStdExtZfh, IsRV64]>; 43def ZfhminExt : ExtInfo<0, [HasStdExtZfhOrZfhmin]>; 44def ZhinxExt : ExtInfo<1, [HasStdExtZhinx]>; 45def ZhinxminExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin]>; 46def Zhinx64Ext : ExtInfo<1, [HasStdExtZhinx, IsRV64]>; 47 48def ZfhminDExt : ExtInfo<0, [HasStdExtZfhOrZfhmin, HasStdExtD]>; 49def ZhinxminZdinxExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx]>; 50 51def H : ExtInfo_r<ZfhExt, FPR16>; 52def H_INX : ExtInfo_r<ZhinxExt, FPR16INX>; 53 54def HH : ExtInfo_rr<ZfhExt, FPR16, FPR16>; 55def HH_INX : ExtInfo_rr<ZhinxExt, FPR16INX, FPR16INX>; 56def XH : ExtInfo_rr<ZfhExt, GPR, FPR16>; 57def XH_INX : ExtInfo_rr<ZhinxExt, GPR, FPR16INX>; 58def HX : ExtInfo_rr<ZfhExt, FPR16, GPR>; 59def HX_INX : ExtInfo_rr<ZhinxExt, FPR16INX, GPR>; 60def XH_64 : ExtInfo_rr<Zfh64Ext, GPR, FPR16>; 61def HX_64 : ExtInfo_rr<Zfh64Ext, FPR16, GPR>; 62def XH_INX_64 : ExtInfo_rr<Zhinx64Ext, GPR, FPR16INX>; 63def HX_INX_64 : ExtInfo_rr<Zhinx64Ext, FPR16INX, GPR>; 64def HFmin : ExtInfo_rr<ZfhminExt, FPR16, FPR32>; 65def HF_INXmin : ExtInfo_rr<ZhinxminExt, FPR16INX, FPR32INX>; 66def HF_INX : ExtInfo_rr<ZhinxExt, FPR16INX, FPR32INX>; 67def FHmin : ExtInfo_rr<ZfhminExt, FPR32, FPR16>; 68def FH_INXmin : ExtInfo_rr<ZhinxminExt, FPR32INX, FPR16INX>; 69def FH_INX : ExtInfo_rr<ZhinxExt, FPR32INX, FPR16INX>; 70def DHmin : ExtInfo_rr<ZfhminDExt, FPR64, FPR16>; 71def DH_INXmin : ExtInfo_rr<ZhinxminZdinxExt, FPR64INX, FPR16INX>; 72def HDmin : ExtInfo_rr<ZfhminDExt, FPR16, FPR64>; 73def HD_INXmin : ExtInfo_rr<ZhinxminZdinxExt, FPR16INX, FPR64INX>; 74 75defvar HINX = [H, H_INX]; 76defvar HHINX = [HH, HH_INX]; 77defvar XHINX = [XH, XH_INX]; 78defvar HXINX = [HX, HX_INX]; 79defvar XHIN64X = [XH_64, XH_INX_64]; 80defvar HXIN64X = [HX_64, HX_INX_64]; 81defvar HFINXmin = [HFmin, HF_INXmin]; 82defvar FHINXmin = [FHmin, FH_INXmin]; 83defvar DHINXmin = [DHmin, DH_INXmin]; 84defvar HDINXmin = [HDmin, HD_INXmin]; 85 86//===----------------------------------------------------------------------===// 87// Instructions 88//===----------------------------------------------------------------------===// 89 90let Predicates = [HasStdExtZfhOrZfhmin] in { 91def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>; 92 93// Operands for stores are in the order srcreg, base, offset rather than 94// reflecting the order these fields are specified in the instruction 95// encoding. 96def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>; 97} // Predicates = [HasStdExtZfhOrZfhmin] 98 99let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in { 100defm FMADD_H : FPFMA_rrr_frm_m<OPC_MADD, 0b10, "fmadd.h", HINX>; 101defm FMSUB_H : FPFMA_rrr_frm_m<OPC_MSUB, 0b10, "fmsub.h", HINX>; 102defm FNMSUB_H : FPFMA_rrr_frm_m<OPC_NMSUB, 0b10, "fnmsub.h", HINX>; 103defm FNMADD_H : FPFMA_rrr_frm_m<OPC_NMADD, 0b10, "fnmadd.h", HINX>; 104} 105 106defm : FPFMADynFrmAlias_m<FMADD_H, "fmadd.h", HINX>; 107defm : FPFMADynFrmAlias_m<FMSUB_H, "fmsub.h", HINX>; 108defm : FPFMADynFrmAlias_m<FNMSUB_H, "fnmsub.h", HINX>; 109defm : FPFMADynFrmAlias_m<FNMADD_H, "fnmadd.h", HINX>; 110 111let SchedRW = [WriteFALU16, ReadFALU16, ReadFALU16] in { 112defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", HINX, /*Commutable*/1>; 113defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", HINX>; 114} 115let SchedRW = [WriteFMul16, ReadFMul16, ReadFMul16] in 116defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", HINX, /*Commutable*/1>; 117 118let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in 119defm FDIV_H : FPALU_rr_frm_m<0b0001110, "fdiv.h", HINX>; 120 121defm : FPALUDynFrmAlias_m<FADD_H, "fadd.h", HINX>; 122defm : FPALUDynFrmAlias_m<FSUB_H, "fsub.h", HINX>; 123defm : FPALUDynFrmAlias_m<FMUL_H, "fmul.h", HINX>; 124defm : FPALUDynFrmAlias_m<FDIV_H, "fdiv.h", HINX>; 125 126defm FSQRT_H : FPUnaryOp_r_frm_m<0b0101110, 0b00000, HHINX, "fsqrt.h">, 127 Sched<[WriteFSqrt16, ReadFSqrt16]>; 128defm : FPUnaryOpDynFrmAlias_m<FSQRT_H, "fsqrt.h", HHINX>; 129 130let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16], 131 mayRaiseFPException = 0 in { 132defm FSGNJ_H : FPALU_rr_m<0b0010010, 0b000, "fsgnj.h", HINX>; 133defm FSGNJN_H : FPALU_rr_m<0b0010010, 0b001, "fsgnjn.h", HINX>; 134defm FSGNJX_H : FPALU_rr_m<0b0010010, 0b010, "fsgnjx.h", HINX>; 135} 136 137let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in { 138defm FMIN_H : FPALU_rr_m<0b0010110, 0b000, "fmin.h", HINX, /*Commutable*/1>; 139defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", HINX, /*Commutable*/1>; 140} 141 142defm FCVT_W_H : FPUnaryOp_r_frm_m<0b1100010, 0b00000, XHINX, "fcvt.w.h">, 143 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; 144defm : FPUnaryOpDynFrmAlias_m<FCVT_W_H, "fcvt.w.h", XHINX>; 145 146defm FCVT_WU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00001, XHINX, "fcvt.wu.h">, 147 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; 148defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_H, "fcvt.wu.h", XHINX>; 149 150defm FCVT_H_W : FPUnaryOp_r_frm_m<0b1101010, 0b00000, HXINX, "fcvt.h.w">, 151 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; 152defm : FPUnaryOpDynFrmAlias_m<FCVT_H_W, "fcvt.h.w", HXINX>; 153 154defm FCVT_H_WU : FPUnaryOp_r_frm_m<0b1101010, 0b00001, HXINX, "fcvt.h.wu">, 155 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; 156defm : FPUnaryOpDynFrmAlias_m<FCVT_H_WU, "fcvt.h.wu", HXINX>; 157 158defm FCVT_H_S : FPUnaryOp_r_frm_m<0b0100010, 0b00000, HFINXmin, "fcvt.h.s">, 159 Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>; 160defm : FPUnaryOpDynFrmAlias_m<FCVT_H_S, "fcvt.h.s", HFINXmin>; 161 162defm FCVT_S_H : FPUnaryOp_r_m<0b0100000, 0b00010, 0b000, FHINXmin, "fcvt.s.h">, 163 Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>; 164 165let Predicates = [HasStdExtZfhOrZfhmin] in { 166let mayRaiseFPException = 0 in 167def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">, 168 Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]>; 169 170let mayRaiseFPException = 0 in 171def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">, 172 Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>; 173} // Predicates = [HasStdExtZfhOrZfhmin] 174 175let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in { 176defm FEQ_H : FPCmp_rr_m<0b1010010, 0b010, "feq.h", HINX, /*Commutable*/1>; 177defm FLT_H : FPCmp_rr_m<0b1010010, 0b001, "flt.h", HINX>; 178defm FLE_H : FPCmp_rr_m<0b1010010, 0b000, "fle.h", HINX>; 179} 180 181let mayRaiseFPException = 0 in 182defm FCLASS_H : FPUnaryOp_r_m<0b1110010, 0b00000, 0b001, XHINX, "fclass.h">, 183 Sched<[WriteFClass16, ReadFClass16]>; 184 185defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, XHIN64X, "fcvt.l.h">, 186 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; 187defm : FPUnaryOpDynFrmAlias_m<FCVT_L_H, "fcvt.l.h", XHIN64X>; 188 189defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, XHIN64X, "fcvt.lu.h">, 190 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; 191defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_H, "fcvt.lu.h", XHIN64X>; 192 193defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, HXIN64X, "fcvt.h.l">, 194 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; 195defm : FPUnaryOpDynFrmAlias_m<FCVT_H_L, "fcvt.h.l", HXIN64X>; 196 197defm FCVT_H_LU : FPUnaryOp_r_frm_m<0b1101010, 0b00011, HXIN64X, "fcvt.h.lu">, 198 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; 199defm : FPUnaryOpDynFrmAlias_m<FCVT_H_LU, "fcvt.h.lu", HXIN64X>; 200 201defm FCVT_H_D : FPUnaryOp_r_frm_m<0b0100010, 0b00001, HDINXmin, "fcvt.h.d">, 202 Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]>; 203defm : FPUnaryOpDynFrmAlias_m<FCVT_H_D, "fcvt.h.d", HDINXmin>; 204 205defm FCVT_D_H : FPUnaryOp_r_m<0b0100001, 0b00010, 0b000, DHINXmin, "fcvt.d.h">, 206 Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]>; 207 208//===----------------------------------------------------------------------===// 209// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 210//===----------------------------------------------------------------------===// 211 212let Predicates = [HasStdExtZfhOrZfhmin] in { 213def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>; 214def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>; 215} // Predicates = [HasStdExtZfhOrZfhmin] 216 217let Predicates = [HasStdExtZfh] in { 218def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 219def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 220def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 221 222// fgt.h/fge.h are recognised by the GNU assembler but the canonical 223// flt.h/fle.h forms will always be printed. Therefore, set a zero weight. 224def : InstAlias<"fgt.h $rd, $rs, $rt", 225 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>; 226def : InstAlias<"fge.h $rd, $rs, $rt", 227 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>; 228} // Predicates = [HasStdExtZfh] 229 230let Predicates = [HasStdExtZfhOrZfhmin] in { 231def PseudoFLH : PseudoFloatLoad<"flh", FPR16>; 232def PseudoFSH : PseudoStore<"fsh", FPR16>; 233let usesCustomInserter = 1 in { 234def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>; 235def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>; 236} 237} // Predicates = [HasStdExtZfhOrZfhmin] 238 239let Predicates = [HasStdExtZhinx] in { 240def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 241def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 242def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 243 244def : InstAlias<"fgt.h $rd, $rs, $rt", 245 (FLT_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>; 246def : InstAlias<"fge.h $rd, $rs, $rt", 247 (FLE_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>; 248} // Predicates = [HasStdExtZhinx] 249 250//===----------------------------------------------------------------------===// 251// Pseudo-instructions and codegen patterns 252//===----------------------------------------------------------------------===// 253 254let Predicates = [HasStdExtZfh] in { 255 256/// Float constants 257def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>; 258def : Pat<(f16 (fpimmneg0)), (FSGNJN_H (FMV_H_X X0), (FMV_H_X X0))>; 259 260/// Float conversion operations 261 262// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 263// are defined later. 264 265/// Float arithmetic operations 266 267def : PatFprFprDynFrm<any_fadd, FADD_H, FPR16>; 268def : PatFprFprDynFrm<any_fsub, FSUB_H, FPR16>; 269def : PatFprFprDynFrm<any_fmul, FMUL_H, FPR16>; 270def : PatFprFprDynFrm<any_fdiv, FDIV_H, FPR16>; 271 272def : Pat<(any_fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>; 273 274def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>; 275def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>; 276 277def : PatFprFpr<fcopysign, FSGNJ_H, FPR16>; 278def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>; 279def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2), 280 (FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>; 281def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>; 282 283// fmadd: rs1 * rs2 + rs3 284def : Pat<(any_fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3), 285 (FMADD_H $rs1, $rs2, $rs3, 0b111)>; 286 287// fmsub: rs1 * rs2 - rs3 288def : Pat<(any_fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3)), 289 (FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; 290 291// fnmsub: -rs1 * rs2 + rs3 292def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3), 293 (FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; 294 295// fnmadd: -rs1 * rs2 - rs3 296def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)), 297 (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; 298 299// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 300def : Pat<(fneg (any_fma_nsz FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)), 301 (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; 302 303// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 304// LLVM's fminnum and fmaxnum 305// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 306def : PatFprFpr<fminnum, FMIN_H, FPR16>; 307def : PatFprFpr<fmaxnum, FMAX_H, FPR16>; 308 309/// Setcc 310// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for 311// strict versions of those. 312 313// Match non-signaling FEQ_D 314def : PatSetCC<FPR16, any_fsetcc, SETEQ, FEQ_H>; 315def : PatSetCC<FPR16, any_fsetcc, SETOEQ, FEQ_H>; 316def : PatSetCC<FPR16, strict_fsetcc, SETLT, PseudoQuietFLT_H>; 317def : PatSetCC<FPR16, strict_fsetcc, SETOLT, PseudoQuietFLT_H>; 318def : PatSetCC<FPR16, strict_fsetcc, SETLE, PseudoQuietFLE_H>; 319def : PatSetCC<FPR16, strict_fsetcc, SETOLE, PseudoQuietFLE_H>; 320 321// Match signaling FEQ_H 322def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETEQ), 323 (AND (FLE_H $rs1, $rs2), 324 (FLE_H $rs2, $rs1))>; 325def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETOEQ), 326 (AND (FLE_H $rs1, $rs2), 327 (FLE_H $rs2, $rs1))>; 328// If both operands are the same, use a single FLE. 329def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETEQ), 330 (FLE_H $rs1, $rs1)>; 331def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETOEQ), 332 (FLE_H $rs1, $rs1)>; 333 334def : PatSetCC<FPR16, any_fsetccs, SETLT, FLT_H>; 335def : PatSetCC<FPR16, any_fsetccs, SETOLT, FLT_H>; 336def : PatSetCC<FPR16, any_fsetccs, SETLE, FLE_H>; 337def : PatSetCC<FPR16, any_fsetccs, SETOLE, FLE_H>; 338 339def Select_FPR16_Using_CC_GPR : SelectCC_rrirr<FPR16, GPR>; 340} // Predicates = [HasStdExtZfh] 341 342let Predicates = [HasStdExtZfhOrZfhmin] in { 343/// Loads 344 345defm : LdPat<load, FLH, f16>; 346 347/// Stores 348 349defm : StPat<store, FSH, FPR16, f16>; 350 351/// Float conversion operations 352 353// f32 -> f16, f16 -> f32 354def : Pat<(any_fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, 0b111)>; 355def : Pat<(any_fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>; 356 357// Moves (no conversion) 358def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>; 359def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>; 360def : Pat<(riscv_fmv_x_signexth FPR16:$src), (FMV_X_H FPR16:$src)>; 361} // Predicates = [HasStdExtZfhOrZfhmin] 362 363let Predicates = [HasStdExtZfh, IsRV32] in { 364// half->[u]int. Round-to-zero must be used. 365def : Pat<(i32 (any_fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>; 366def : Pat<(i32 (any_fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>; 367 368// Saturating float->[u]int32. 369def : Pat<(i32 (riscv_fcvt_x FPR16:$rs1, timm:$frm)), (FCVT_W_H $rs1, timm:$frm)>; 370def : Pat<(i32 (riscv_fcvt_xu FPR16:$rs1, timm:$frm)), (FCVT_WU_H $rs1, timm:$frm)>; 371 372// half->int32 with current rounding mode. 373def : Pat<(i32 (any_lrint FPR16:$rs1)), (FCVT_W_H $rs1, 0b111)>; 374 375// half->int32 rounded to nearest with ties rounded away from zero. 376def : Pat<(i32 (any_lround FPR16:$rs1)), (FCVT_W_H $rs1, 0b100)>; 377 378// [u]int->half. Match GCC and default to using dynamic rounding mode. 379def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>; 380def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>; 381} // Predicates = [HasStdExtZfh, IsRV32] 382 383let Predicates = [HasStdExtZfh, IsRV64] in { 384// Use target specific isd nodes to help us remember the result is sign 385// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 386// duplicated if it has another user that didn't need the sign_extend. 387def : Pat<(riscv_any_fcvt_w_rv64 FPR16:$rs1, timm:$frm), (FCVT_W_H $rs1, timm:$frm)>; 388def : Pat<(riscv_any_fcvt_wu_rv64 FPR16:$rs1, timm:$frm), (FCVT_WU_H $rs1, timm:$frm)>; 389 390// half->[u]int64. Round-to-zero must be used. 391def : Pat<(i64 (any_fp_to_sint FPR16:$rs1)), (FCVT_L_H $rs1, 0b001)>; 392def : Pat<(i64 (any_fp_to_uint FPR16:$rs1)), (FCVT_LU_H $rs1, 0b001)>; 393 394// Saturating float->[u]int64. 395def : Pat<(i64 (riscv_fcvt_x FPR16:$rs1, timm:$frm)), (FCVT_L_H $rs1, timm:$frm)>; 396def : Pat<(i64 (riscv_fcvt_xu FPR16:$rs1, timm:$frm)), (FCVT_LU_H $rs1, timm:$frm)>; 397 398// half->int64 with current rounding mode. 399def : Pat<(i64 (any_lrint FPR16:$rs1)), (FCVT_L_H $rs1, 0b111)>; 400def : Pat<(i64 (any_llrint FPR16:$rs1)), (FCVT_L_H $rs1, 0b111)>; 401 402// half->int64 rounded to nearest with ties rounded away from zero. 403def : Pat<(i64 (any_lround FPR16:$rs1)), (FCVT_L_H $rs1, 0b100)>; 404def : Pat<(i64 (any_llround FPR16:$rs1)), (FCVT_L_H $rs1, 0b100)>; 405 406// [u]int->fp. Match GCC and default to using dynamic rounding mode. 407def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W $rs1, 0b111)>; 408def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, 0b111)>; 409def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, 0b111)>; 410def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, 0b111)>; 411} // Predicates = [HasStdExtZfh, IsRV64] 412 413let Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] in { 414/// Float conversion operations 415// f64 -> f16, f16 -> f64 416def : Pat<(any_fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>; 417def : Pat<(any_fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>; 418 419/// Float arithmetic operations 420def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2), 421 (FSGNJ_H $rs1, (FCVT_H_D $rs2, 0b111))>; 422def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>; 423} // Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] 424