1//===-- RISCVInstrInfoZfh.td - RISC-V 'Zfh' instructions ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'Zfh' 10// half-precision floating-point extension, version 1.0. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVFMV_H_X 19 : SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>; 20def SDT_RISCVFMV_X_ANYEXTH 21 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>; 22 23def riscv_fmv_h_x 24 : SDNode<"RISCVISD::FMV_H_X", SDT_RISCVFMV_H_X>; 25def riscv_fmv_x_anyexth 26 : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_ANYEXTH>; 27 28//===----------------------------------------------------------------------===// 29// Operand and SDNode transformation definitions. 30//===----------------------------------------------------------------------===// 31 32// Zhinxmin and Zhinx 33 34def FPR16INX : RegisterOperand<GPRF16> { 35 let ParserMatchClass = GPRAsFPR; 36 let DecoderMethod = "DecodeGPRRegisterClass"; 37} 38 39def ZfhExt : ExtInfo<0, [HasStdExtZfh]>; 40def Zfh64Ext : ExtInfo<0, [HasStdExtZfh, IsRV64]>; 41def ZfhminExt : ExtInfo<0, [HasStdExtZfhOrZfhmin]>; 42def ZhinxExt : ExtInfo<1, [HasStdExtZhinx]>; 43def ZhinxminExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin]>; 44def Zhinx64Ext : ExtInfo<1, [HasStdExtZhinx, IsRV64]>; 45 46def ZfhminDExt : ExtInfo<0, [HasStdExtZfhOrZfhmin, HasStdExtD]>; 47def ZhinxminZdinxExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx]>; 48 49def H : ExtInfo_r<ZfhExt, FPR16>; 50def H_INX : ExtInfo_r<ZhinxExt, FPR16INX>; 51 52def HH : ExtInfo_rr<ZfhExt, FPR16, FPR16>; 53def HH_INX : ExtInfo_rr<ZhinxExt, FPR16INX, FPR16INX>; 54def XH : ExtInfo_rr<ZfhExt, GPR, FPR16>; 55def XH_INX : ExtInfo_rr<ZhinxExt, GPR, FPR16INX>; 56def HX : ExtInfo_rr<ZfhExt, FPR16, GPR>; 57def HX_INX : ExtInfo_rr<ZhinxExt, FPR16INX, GPR>; 58def XH_64 : ExtInfo_rr<Zfh64Ext, GPR, FPR16>; 59def HX_64 : ExtInfo_rr<Zfh64Ext, FPR16, GPR>; 60def XH_INX_64 : ExtInfo_rr<Zhinx64Ext, GPR, FPR16INX>; 61def HX_INX_64 : ExtInfo_rr<Zhinx64Ext, FPR16INX, GPR>; 62def HFmin : ExtInfo_rr<ZfhminExt, FPR16, FPR32>; 63def HF_INXmin : ExtInfo_rr<ZhinxminExt, FPR16INX, FPR32INX>; 64def HF_INX : ExtInfo_rr<ZhinxExt, FPR16INX, FPR32INX>; 65def FHmin : ExtInfo_rr<ZfhminExt, FPR32, FPR16>; 66def FH_INXmin : ExtInfo_rr<ZhinxminExt, FPR32INX, FPR16INX>; 67def FH_INX : ExtInfo_rr<ZhinxExt, FPR32INX, FPR16INX>; 68def DHmin : ExtInfo_rr<ZfhminDExt, FPR64, FPR16>; 69def DH_INXmin : ExtInfo_rr<ZhinxminZdinxExt, FPR64INX, FPR16INX>; 70def HDmin : ExtInfo_rr<ZfhminDExt, FPR16, FPR64>; 71def HD_INXmin : ExtInfo_rr<ZhinxminZdinxExt, FPR16INX, FPR64INX>; 72 73defvar HINX = [H, H_INX]; 74defvar HHINX = [HH, HH_INX]; 75defvar XHINX = [XH, XH_INX]; 76defvar HXINX = [HX, HX_INX]; 77defvar XHIN64X = [XH_64, XH_INX_64]; 78defvar HXIN64X = [HX_64, HX_INX_64]; 79defvar HFINXmin = [HFmin, HF_INXmin]; 80defvar FHINXmin = [FHmin, FH_INXmin]; 81defvar DHINXmin = [DHmin, DH_INXmin]; 82defvar HDINXmin = [HDmin, HD_INXmin]; 83 84//===----------------------------------------------------------------------===// 85// Instructions 86//===----------------------------------------------------------------------===// 87 88let Predicates = [HasStdExtZfhOrZfhmin] in { 89def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>; 90 91// Operands for stores are in the order srcreg, base, offset rather than 92// reflecting the order these fields are specified in the instruction 93// encoding. 94def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>; 95} // Predicates = [HasStdExtZfhOrZfhmin] 96 97let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in { 98defm FMADD_H : FPFMA_rrr_frm_m<OPC_MADD, 0b10, "fmadd.h", HINX>; 99defm FMSUB_H : FPFMA_rrr_frm_m<OPC_MSUB, 0b10, "fmsub.h", HINX>; 100defm FNMSUB_H : FPFMA_rrr_frm_m<OPC_NMSUB, 0b10, "fnmsub.h", HINX>; 101defm FNMADD_H : FPFMA_rrr_frm_m<OPC_NMADD, 0b10, "fnmadd.h", HINX>; 102} 103 104defm : FPFMADynFrmAlias_m<FMADD_H, "fmadd.h", HINX>; 105defm : FPFMADynFrmAlias_m<FMSUB_H, "fmsub.h", HINX>; 106defm : FPFMADynFrmAlias_m<FNMSUB_H, "fnmsub.h", HINX>; 107defm : FPFMADynFrmAlias_m<FNMADD_H, "fnmadd.h", HINX>; 108 109let SchedRW = [WriteFALU16, ReadFALU16, ReadFALU16] in { 110defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", HINX>; 111defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", HINX>; 112} 113let SchedRW = [WriteFMul16, ReadFMul16, ReadFMul16] in 114defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", HINX>; 115 116let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in 117defm FDIV_H : FPALU_rr_frm_m<0b0001110, "fdiv.h", HINX>; 118 119defm : FPALUDynFrmAlias_m<FADD_H, "fadd.h", HINX>; 120defm : FPALUDynFrmAlias_m<FSUB_H, "fsub.h", HINX>; 121defm : FPALUDynFrmAlias_m<FMUL_H, "fmul.h", HINX>; 122defm : FPALUDynFrmAlias_m<FDIV_H, "fdiv.h", HINX>; 123 124defm FSQRT_H : FPUnaryOp_r_frm_m<0b0101110, 0b00000, HHINX, "fsqrt.h">, 125 Sched<[WriteFSqrt16, ReadFSqrt16]>; 126defm : FPUnaryOpDynFrmAlias_m<FSQRT_H, "fsqrt.h", HHINX>; 127 128let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16], 129 mayRaiseFPException = 0 in { 130defm FSGNJ_H : FPALU_rr_m<0b0010010, 0b000, "fsgnj.h", HINX>; 131defm FSGNJN_H : FPALU_rr_m<0b0010010, 0b001, "fsgnjn.h", HINX>; 132defm FSGNJX_H : FPALU_rr_m<0b0010010, 0b010, "fsgnjx.h", HINX>; 133} 134 135let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in { 136defm FMIN_H : FPALU_rr_m<0b0010110, 0b000, "fmin.h", HINX>; 137defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", HINX>; 138} 139 140defm FCVT_W_H : FPUnaryOp_r_frm_m<0b1100010, 0b00000, XHINX, "fcvt.w.h">, 141 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; 142defm : FPUnaryOpDynFrmAlias_m<FCVT_W_H, "fcvt.w.h", XHINX>; 143 144defm FCVT_WU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00001, XHINX, "fcvt.wu.h">, 145 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; 146defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_H, "fcvt.wu.h", XHINX>; 147 148defm FCVT_H_W : FPUnaryOp_r_frm_m<0b1101010, 0b00000, HXINX, "fcvt.h.w">, 149 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; 150defm : FPUnaryOpDynFrmAlias_m<FCVT_H_W, "fcvt.h.w", HXINX>; 151 152defm FCVT_H_WU : FPUnaryOp_r_frm_m<0b1101010, 0b00001, HXINX, "fcvt.h.wu">, 153 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; 154defm : FPUnaryOpDynFrmAlias_m<FCVT_H_WU, "fcvt.h.wu", HXINX>; 155 156defm FCVT_H_S : FPUnaryOp_r_frm_m<0b0100010, 0b00000, HFINXmin, "fcvt.h.s">, 157 Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>; 158defm : FPUnaryOpDynFrmAlias_m<FCVT_H_S, "fcvt.h.s", HFINXmin>; 159 160defm FCVT_S_H : FPUnaryOp_r_m<0b0100000, 0b00010, 0b000, FHINXmin, "fcvt.s.h">, 161 Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>; 162 163let Predicates = [HasStdExtZfhOrZfhmin] in { 164let mayRaiseFPException = 0 in 165def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">, 166 Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]>; 167 168let mayRaiseFPException = 0 in 169def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">, 170 Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>; 171} // Predicates = [HasStdExtZfhOrZfhmin] 172 173let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in { 174defm FEQ_H : FPCmp_rr_m<0b1010010, 0b010, "feq.h", HINX>; 175defm FLT_H : FPCmp_rr_m<0b1010010, 0b001, "flt.h", HINX>; 176defm FLE_H : FPCmp_rr_m<0b1010010, 0b000, "fle.h", HINX>; 177} 178 179let mayRaiseFPException = 0 in 180defm FCLASS_H : FPUnaryOp_r_m<0b1110010, 0b00000, 0b001, XHINX, "fclass.h">, 181 Sched<[WriteFClass16, ReadFClass16]>; 182 183defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, XHIN64X, "fcvt.l.h">, 184 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; 185defm : FPUnaryOpDynFrmAlias_m<FCVT_L_H, "fcvt.l.h", XHIN64X>; 186 187defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, XHIN64X, "fcvt.lu.h">, 188 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; 189defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_H, "fcvt.lu.h", XHIN64X>; 190 191defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, HXIN64X, "fcvt.h.l">, 192 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; 193defm : FPUnaryOpDynFrmAlias_m<FCVT_H_L, "fcvt.h.l", HXIN64X>; 194 195defm FCVT_H_LU : FPUnaryOp_r_frm_m<0b1101010, 0b00011, HXIN64X, "fcvt.h.lu">, 196 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; 197defm : FPUnaryOpDynFrmAlias_m<FCVT_H_LU, "fcvt.h.lu", HXIN64X>; 198 199defm FCVT_H_D : FPUnaryOp_r_frm_m<0b0100010, 0b00001, HDINXmin, "fcvt.h.d">, 200 Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]>; 201defm : FPUnaryOpDynFrmAlias_m<FCVT_H_D, "fcvt.h.d", HDINXmin>; 202 203defm FCVT_D_H : FPUnaryOp_r_m<0b0100001, 0b00010, 0b000, DHINXmin, "fcvt.d.h">, 204 Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]>; 205 206//===----------------------------------------------------------------------===// 207// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 208//===----------------------------------------------------------------------===// 209 210let Predicates = [HasStdExtZfhOrZfhmin] in { 211def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>; 212def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>; 213} // Predicates = [HasStdExtZfhOrZfhmin] 214 215let Predicates = [HasStdExtZfh] in { 216def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 217def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 218def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 219 220// fgt.h/fge.h are recognised by the GNU assembler but the canonical 221// flt.h/fle.h forms will always be printed. Therefore, set a zero weight. 222def : InstAlias<"fgt.h $rd, $rs, $rt", 223 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>; 224def : InstAlias<"fge.h $rd, $rs, $rt", 225 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>; 226} // Predicates = [HasStdExtZfh] 227 228let Predicates = [HasStdExtZfhOrZfhmin] in { 229def PseudoFLH : PseudoFloatLoad<"flh", FPR16>; 230def PseudoFSH : PseudoStore<"fsh", FPR16>; 231let usesCustomInserter = 1 in { 232def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>; 233def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>; 234} 235} // Predicates = [HasStdExtZfhOrZfhmin] 236 237let Predicates = [HasStdExtZhinx] in { 238def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 239def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 240def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 241 242def : InstAlias<"fgt.h $rd, $rs, $rt", 243 (FLT_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>; 244def : InstAlias<"fge.h $rd, $rs, $rt", 245 (FLE_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>; 246} // Predicates = [HasStdExtZhinx] 247 248//===----------------------------------------------------------------------===// 249// Pseudo-instructions and codegen patterns 250//===----------------------------------------------------------------------===// 251 252/// Generic pattern classes 253class PatFpr16Fpr16<SDPatternOperator OpNode, RVInstR Inst> 254 : Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2)>; 255 256class PatFpr16Fpr16DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 257 : Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2, 0b111)>; 258 259let Predicates = [HasStdExtZfh] in { 260 261/// Float constants 262def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>; 263def : Pat<(f16 (fpimmneg0)), (FSGNJN_H (FMV_H_X X0), (FMV_H_X X0))>; 264 265/// Float conversion operations 266 267// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 268// are defined later. 269 270/// Float arithmetic operations 271 272def : PatFpr16Fpr16DynFrm<any_fadd, FADD_H>; 273def : PatFpr16Fpr16DynFrm<any_fsub, FSUB_H>; 274def : PatFpr16Fpr16DynFrm<any_fmul, FMUL_H>; 275def : PatFpr16Fpr16DynFrm<any_fdiv, FDIV_H>; 276 277def : Pat<(any_fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>; 278 279def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>; 280def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>; 281 282def : PatFpr16Fpr16<fcopysign, FSGNJ_H>; 283def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>; 284def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2), 285 (FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>; 286def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>; 287 288// fmadd: rs1 * rs2 + rs3 289def : Pat<(any_fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3), 290 (FMADD_H $rs1, $rs2, $rs3, 0b111)>; 291 292// fmsub: rs1 * rs2 - rs3 293def : Pat<(any_fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3)), 294 (FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; 295 296// fnmsub: -rs1 * rs2 + rs3 297def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3), 298 (FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; 299 300// fnmadd: -rs1 * rs2 - rs3 301def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)), 302 (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; 303 304// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 305// LLVM's fminnum and fmaxnum 306// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 307def : PatFpr16Fpr16<fminnum, FMIN_H>; 308def : PatFpr16Fpr16<fmaxnum, FMAX_H>; 309 310/// Setcc 311// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for 312// strict versions of those. 313 314// Match non-signaling FEQ_D 315def : PatSetCC<FPR16, any_fsetcc, SETEQ, FEQ_H>; 316def : PatSetCC<FPR16, any_fsetcc, SETOEQ, FEQ_H>; 317def : PatSetCC<FPR16, strict_fsetcc, SETLT, PseudoQuietFLT_H>; 318def : PatSetCC<FPR16, strict_fsetcc, SETOLT, PseudoQuietFLT_H>; 319def : PatSetCC<FPR16, strict_fsetcc, SETLE, PseudoQuietFLE_H>; 320def : PatSetCC<FPR16, strict_fsetcc, SETOLE, PseudoQuietFLE_H>; 321 322// Match signaling FEQ_H 323def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETEQ), 324 (AND (FLE_H $rs1, $rs2), 325 (FLE_H $rs2, $rs1))>; 326def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETOEQ), 327 (AND (FLE_H $rs1, $rs2), 328 (FLE_H $rs2, $rs1))>; 329// If both operands are the same, use a single FLE. 330def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETEQ), 331 (FLE_H $rs1, $rs1)>; 332def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETOEQ), 333 (FLE_H $rs1, $rs1)>; 334 335def : PatSetCC<FPR16, any_fsetccs, SETLT, FLT_H>; 336def : PatSetCC<FPR16, any_fsetccs, SETOLT, FLT_H>; 337def : PatSetCC<FPR16, any_fsetccs, SETLE, FLE_H>; 338def : PatSetCC<FPR16, any_fsetccs, SETOLE, FLE_H>; 339 340def Select_FPR16_Using_CC_GPR : SelectCC_rrirr<FPR16, GPR>; 341} // Predicates = [HasStdExtZfh] 342 343let Predicates = [HasStdExtZfhOrZfhmin] in { 344/// Loads 345 346defm : LdPat<load, FLH, f16>; 347 348/// Stores 349 350defm : StPat<store, FSH, FPR16, f16>; 351 352/// Float conversion operations 353 354// f32 -> f16, f16 -> f32 355def : Pat<(any_fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, 0b111)>; 356def : Pat<(any_fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>; 357 358// Moves (no conversion) 359def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>; 360def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>; 361} // Predicates = [HasStdExtZfhOrZfhmin] 362 363let Predicates = [HasStdExtZfh, IsRV32] in { 364// half->[u]int. Round-to-zero must be used. 365def : Pat<(i32 (any_fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>; 366def : Pat<(i32 (any_fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>; 367 368// Saturating float->[u]int32. 369def : Pat<(i32 (riscv_fcvt_x FPR16:$rs1, timm:$frm)), (FCVT_W_H $rs1, timm:$frm)>; 370def : Pat<(i32 (riscv_fcvt_xu FPR16:$rs1, timm:$frm)), (FCVT_WU_H $rs1, timm:$frm)>; 371 372// half->int32 with current rounding mode. 373def : Pat<(i32 (any_lrint FPR16:$rs1)), (FCVT_W_H $rs1, 0b111)>; 374 375// half->int32 rounded to nearest with ties rounded away from zero. 376def : Pat<(i32 (any_lround FPR16:$rs1)), (FCVT_W_H $rs1, 0b100)>; 377 378// [u]int->half. Match GCC and default to using dynamic rounding mode. 379def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>; 380def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>; 381} // Predicates = [HasStdExtZfh, IsRV32] 382 383let Predicates = [HasStdExtZfh, IsRV64] in { 384// Use target specific isd nodes to help us remember the result is sign 385// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 386// duplicated if it has another user that didn't need the sign_extend. 387def : Pat<(riscv_any_fcvt_w_rv64 FPR16:$rs1, timm:$frm), (FCVT_W_H $rs1, timm:$frm)>; 388def : Pat<(riscv_any_fcvt_wu_rv64 FPR16:$rs1, timm:$frm), (FCVT_WU_H $rs1, timm:$frm)>; 389 390// half->[u]int64. Round-to-zero must be used. 391def : Pat<(i64 (any_fp_to_sint FPR16:$rs1)), (FCVT_L_H $rs1, 0b001)>; 392def : Pat<(i64 (any_fp_to_uint FPR16:$rs1)), (FCVT_LU_H $rs1, 0b001)>; 393 394// Saturating float->[u]int64. 395def : Pat<(i64 (riscv_fcvt_x FPR16:$rs1, timm:$frm)), (FCVT_L_H $rs1, timm:$frm)>; 396def : Pat<(i64 (riscv_fcvt_xu FPR16:$rs1, timm:$frm)), (FCVT_LU_H $rs1, timm:$frm)>; 397 398// half->int64 with current rounding mode. 399def : Pat<(i64 (any_lrint FPR16:$rs1)), (FCVT_L_H $rs1, 0b111)>; 400def : Pat<(i64 (any_llrint FPR16:$rs1)), (FCVT_L_H $rs1, 0b111)>; 401 402// half->int64 rounded to nearest with ties rounded away from zero. 403def : Pat<(i64 (any_lround FPR16:$rs1)), (FCVT_L_H $rs1, 0b100)>; 404def : Pat<(i64 (any_llround FPR16:$rs1)), (FCVT_L_H $rs1, 0b100)>; 405 406// [u]int->fp. Match GCC and default to using dynamic rounding mode. 407def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W $rs1, 0b111)>; 408def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, 0b111)>; 409def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, 0b111)>; 410def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, 0b111)>; 411} // Predicates = [HasStdExtZfh, IsRV64] 412 413let Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] in { 414/// Float conversion operations 415// f64 -> f16, f16 -> f64 416def : Pat<(any_fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>; 417def : Pat<(any_fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>; 418 419/// Float arithmetic operations 420def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2), 421 (FSGNJ_H $rs1, (FCVT_H_D $rs2, 0b111))>; 422def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>; 423} // Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] 424