xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td (revision e53a21abdf2953714e44e3c54b4bb78557cb096c)
1//===-- RISCVInstrInfoZc.td - RISC-V 'Zc*' instructions ----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This file describes the RISC-V instructions from the 'Zc*' compressed
10/// instruction extensions, version 1.0.3.
11///
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Operand and SDNode transformation definitions.
16//===----------------------------------------------------------------------===//
17
18def uimm2_lsb0 : RISCVOp,
19                 ImmLeaf<XLenVT, [{return isShiftedUInt<1, 1>(Imm);}]> {
20  let ParserMatchClass = UImmAsmOperand<2, "Lsb0">;
21  let EncoderMethod = "getImmOpValue";
22  let DecoderMethod = "decodeUImmOperand<2>";
23  let OperandType = "OPERAND_UIMM2_LSB0";
24  let MCOperandPredicate = [{
25    int64_t Imm;
26    if (!MCOp.evaluateAsConstantImm(Imm))
27      return false;
28    return isShiftedUInt<1, 1>(Imm);
29  }];
30}
31
32def uimm8ge32 : RISCVOp {
33  let ParserMatchClass = UImmAsmOperand<8, "GE32">;
34  let DecoderMethod = "decodeUImmOperand<8>";
35  let OperandType = "OPERAND_UIMM8_GE32";
36}
37
38def RlistAsmOperand : AsmOperandClass {
39  let Name = "Rlist";
40  let ParserMethod = "parseReglist";
41  let DiagnosticType = "InvalidRlist";
42}
43
44def StackAdjAsmOperand : AsmOperandClass {
45  let Name = "StackAdj";
46  let ParserMethod = "parseZcmpStackAdj";
47  let DiagnosticType = "InvalidStackAdj";
48  let PredicateMethod = "isSpimm";
49  let RenderMethod = "addSpimmOperands";
50}
51
52def NegStackAdjAsmOperand : AsmOperandClass {
53  let Name = "NegStackAdj";
54  let ParserMethod = "parseZcmpNegStackAdj";
55  let DiagnosticType = "InvalidStackAdj";
56  let PredicateMethod = "isSpimm";
57  let RenderMethod = "addSpimmOperands";
58}
59
60def rlist : Operand<OtherVT> {
61   let ParserMatchClass = RlistAsmOperand;
62   let PrintMethod = "printRlist";
63   let DecoderMethod = "decodeZcmpRlist";
64   let EncoderMethod = "getRlistOpValue";
65   let MCOperandPredicate = [{
66    int64_t Imm;
67    if (!MCOp.evaluateAsConstantImm(Imm))
68      return false;
69    // 0~3 Reserved for EABI
70    return isUInt<4>(Imm) && Imm >= 4;
71  }];
72}
73
74def stackadj : RISCVOp<OtherVT> {
75  let ParserMatchClass = StackAdjAsmOperand;
76  let PrintMethod = "printStackAdj";
77  let DecoderMethod = "decodeZcmpSpimm";
78  let OperandType = "OPERAND_SPIMM";
79  let MCOperandPredicate = [{
80    int64_t Imm;
81    if (!MCOp.evaluateAsConstantImm(Imm))
82      return false;
83    return isShiftedUInt<2, 4>(Imm);
84  }];
85}
86
87def negstackadj : RISCVOp<OtherVT> {
88  let ParserMatchClass = NegStackAdjAsmOperand;
89  let PrintMethod = "printNegStackAdj";
90  let DecoderMethod = "decodeZcmpSpimm";
91  let OperandType = "OPERAND_SPIMM";
92  let MCOperandPredicate = [{
93    int64_t Imm;
94    if (!MCOp.evaluateAsConstantImm(Imm))
95      return false;
96    return isShiftedUInt<2, 4>(Imm);
97  }];
98}
99
100//===----------------------------------------------------------------------===//
101// Instruction Class Templates
102//===----------------------------------------------------------------------===//
103
104let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
105class CLoadB_ri<bits<6> funct6, string OpcodeStr>
106    : RVInst16CLB<funct6, 0b00, (outs GPRC:$rd),
107                  (ins GPRCMem:$rs1, uimm2:$imm),
108                  OpcodeStr, "$rd, ${imm}(${rs1})"> {
109  bits<2> imm;
110
111  let Inst{6-5} = imm{0,1};
112}
113
114let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
115class CLoadH_ri<bits<6> funct6, bit funct1, string OpcodeStr>
116    : RVInst16CLH<funct6, funct1, 0b00, (outs GPRC:$rd),
117                  (ins GPRCMem:$rs1, uimm2_lsb0:$imm),
118                  OpcodeStr, "$rd, ${imm}(${rs1})"> {
119  bits<2> imm;
120
121  let Inst{5} = imm{1};
122}
123
124let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
125class CStoreB_rri<bits<6> funct6, string OpcodeStr>
126    : RVInst16CSB<funct6, 0b00, (outs),
127                  (ins GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
128                  OpcodeStr, "$rs2, ${imm}(${rs1})"> {
129  bits<2> imm;
130
131  let Inst{6-5} = imm{0,1};
132}
133
134let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
135class CStoreH_rri<bits<6> funct6, bit funct1, string OpcodeStr>
136    : RVInst16CSH<funct6, funct1, 0b00, (outs),
137                  (ins GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
138                  OpcodeStr, "$rs2, ${imm}(${rs1})"> {
139  bits<2> imm;
140
141  let Inst{5} = imm{1};
142}
143
144let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
145class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
146  RVInst16CU<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
147             OpcodeStr, "$rd"> {
148  let Constraints = "$rd = $rd_wb";
149}
150
151class RVInstZcCPPP<bits<5> funct5, string opcodestr,
152                   DAGOperand immtype = stackadj>
153    : RVInst16<(outs), (ins rlist:$rlist, immtype:$stackadj),
154               opcodestr, "$rlist, $stackadj", [], InstFormatOther> {
155  bits<4> rlist;
156  bits<16> stackadj;
157
158  let Inst{1-0} = 0b10;
159  let Inst{3-2} = stackadj{5-4};
160  let Inst{7-4} = rlist;
161  let Inst{12-8} = funct5;
162  let Inst{15-13} = 0b101;
163}
164
165//===----------------------------------------------------------------------===//
166// Instructions
167//===----------------------------------------------------------------------===//
168
169let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in
170def C_ZEXT_W  : RVZcArith_r<0b11100 , "c.zext.w">,
171                Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
172
173let Predicates = [HasStdExtZcb, HasStdExtZbb] in {
174def C_ZEXT_H  : RVZcArith_r<0b11010 , "c.zext.h">,
175                Sched<[WriteIALU, ReadIALU]>;
176def C_SEXT_B  : RVZcArith_r<0b11001 , "c.sext.b">,
177                Sched<[WriteIALU, ReadIALU]>;
178def C_SEXT_H  : RVZcArith_r<0b11011 , "c.sext.h">,
179                Sched<[WriteIALU, ReadIALU]>;
180}
181
182let Predicates = [HasStdExtZcb] in
183def C_ZEXT_B  : RVZcArith_r<0b11000 , "c.zext.b">,
184                Sched<[WriteIALU, ReadIALU]>;
185
186let Predicates = [HasStdExtZcb, HasStdExtZmmul] in
187def C_MUL     : CA_ALU<0b100111, 0b10, "c.mul", GPRC>,
188                Sched<[WriteIMul, ReadIMul, ReadIMul]>;
189
190let Predicates = [HasStdExtZcb] in {
191def C_NOT : RVZcArith_r<0b11101 , "c.not">,
192            Sched<[WriteIALU, ReadIALU]>;
193
194def C_LBU : CLoadB_ri<0b100000, "c.lbu">,
195            Sched<[WriteLDB, ReadMemBase]>;
196def C_LHU : CLoadH_ri<0b100001, 0b0, "c.lhu">,
197            Sched<[WriteLDH, ReadMemBase]>;
198def C_LH  : CLoadH_ri<0b100001, 0b1, "c.lh">,
199            Sched<[WriteLDH, ReadMemBase]>;
200
201def C_SB : CStoreB_rri<0b100010, "c.sb">,
202           Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
203def C_SH : CStoreH_rri<0b100011, 0b0, "c.sh">,
204           Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
205}
206
207// Zcmp
208let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp],
209    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
210let Defs = [X10, X11] in
211def CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),
212                            (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">,
213                Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
214
215let Uses = [X10, X11] in
216def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
217                            (ins), "cm.mvsa01", "$rs1, $rs2">,
218                Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
219} // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]...
220
221let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp] in {
222let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2] in
223def CM_PUSH : RVInstZcCPPP<0b11000, "cm.push", negstackadj>,
224              Sched<[WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,
225                     ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
226                     ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
227                     ReadStoreData, ReadStoreData, ReadStoreData]>;
228
229let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
230    Uses = [X2], Defs = [X2] in
231def CM_POPRET : RVInstZcCPPP<0b11110, "cm.popret">,
232                Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
233                       WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
234                       WriteLDW, WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
235
236let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
237    Uses = [X2], Defs = [X2, X10] in
238def CM_POPRETZ : RVInstZcCPPP<0b11100, "cm.popretz">,
239                 Sched<[WriteIALU, WriteIALU, WriteLDW, WriteLDW, WriteLDW,
240                        WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
241                        WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
242                        ReadIALU]>;
243
244let hasSideEffects = 0, mayLoad = 1, mayStore = 0,
245    Uses = [X2], Defs = [X2] in
246def CM_POP : RVInstZcCPPP<0b11010, "cm.pop">,
247             Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
248                    WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
249                    WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
250} // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]...
251
252let DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt],
253    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
254def CM_JT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm5:$index),
255                       "cm.jt", "$index">{
256  bits<5> index;
257
258  let Inst{12-7} = 0b000000;
259  let Inst{6-2} = index;
260}
261
262let Defs = [X1] in
263def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index),
264                         "cm.jalt", "$index">{
265  bits<8> index;
266
267  let Inst{12-10} = 0b000;
268  let Inst{9-2} = index;
269}
270} // DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt]...
271
272
273let Predicates = [HasStdExtZcb, HasStdExtZmmul] in{
274def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
275                  (C_MUL GPRC:$rs1, GPRC:$rs2)>;
276let isCompressOnly = true in
277def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
278                  (C_MUL GPRC:$rs1, GPRC:$rs2)>;
279} // Predicates = [HasStdExtZcb, HasStdExtZmmul]
280
281let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
282def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),
283                  (C_SEXT_B GPRC:$rs1, GPRC:$rs1)>;
284def : CompressPat<(SEXT_H GPRC:$rs1, GPRC:$rs1),
285                  (C_SEXT_H GPRC:$rs1, GPRC:$rs1)>;
286} // Predicates = [HasStdExtZcb, HasStdExtZbb]
287
288let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
289def : CompressPat<(ZEXT_H_RV32 GPRC:$rs1, GPRC:$rs1),
290                  (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
291def : CompressPat<(ZEXT_H_RV64 GPRC:$rs1, GPRC:$rs1),
292                  (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
293} // Predicates = [HasStdExtZcb, HasStdExtZbb]
294
295let Predicates = [HasStdExtZcb] in{
296def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, 255),
297                  (C_ZEXT_B GPRC:$rs1, GPRC:$rs1)>;
298} // Predicates = [HasStdExtZcb]
299
300let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{
301def : CompressPat<(ADD_UW GPRC:$rs1, GPRC:$rs1, X0),
302                  (C_ZEXT_W GPRC:$rs1, GPRC:$rs1)>;
303} // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64]
304
305let Predicates = [HasStdExtZcb] in{
306def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
307                  (C_NOT GPRC:$rs1, GPRC:$rs1)>;
308}
309
310let Predicates = [HasStdExtZcb] in{
311def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm),
312                  (C_LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm)>;
313def : CompressPat<(LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
314                  (C_LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
315def : CompressPat<(LH GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
316                  (C_LH GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
317def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
318                  (C_SB GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm)>;
319def : CompressPat<(SH GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
320                  (C_SH GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
321}// Predicates = [HasStdExtZcb]
322
323
324//===----------------------------------------------------------------------===//
325// Pseudo Instructions
326//===----------------------------------------------------------------------===//
327
328let Predicates = [HasStdExtZcb] in {
329def : InstAlias<"c.lbu $rd, (${rs1})",(C_LBU GPRC:$rd, GPRC:$rs1, 0), 0>;
330def : InstAlias<"c.lhu $rd, (${rs1})",(C_LHU GPRC:$rd, GPRC:$rs1, 0), 0>;
331def : InstAlias<"c.lh $rd, (${rs1})", (C_LH GPRC:$rd, GPRC:$rs1, 0), 0>;
332def : InstAlias<"c.sb $rd, (${rs1})", (C_SB GPRC:$rd, GPRC:$rs1, 0), 0>;
333def : InstAlias<"c.sh $rd, (${rs1})", (C_SH GPRC:$rd, GPRC:$rs1, 0), 0>;
334}
335