1//===-- RISCVInstrInfoZalasr.td ---------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the Zalasr (Load-Acquire 10// and Store-Release) extension 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction class templates 16//===----------------------------------------------------------------------===// 17 18let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 19class LAQ_r<bit aq, bit rl, bits<3> funct3, string opcodestr> 20 : RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO, 21 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1), 22 opcodestr, "$rd, $rs1"> { 23 let rs2 = 0; 24} 25 26let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 27class SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr> 28 : RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO, 29 (outs ), (ins GPRMemZeroOffset:$rs1, GPR:$rs2), 30 opcodestr, "$rs2, $rs1"> { 31 let rd = 0; 32} 33multiclass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> { 34 def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">; 35 def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">; 36} 37 38multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> { 39 def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">; 40 def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">; 41} 42 43//===----------------------------------------------------------------------===// 44// Instructions 45//===----------------------------------------------------------------------===// 46 47let Predicates = [HasStdExtZalasr] in { 48defm LB : LAQ_r_aq_rl<0b000, "lb">; 49defm LH : LAQ_r_aq_rl<0b001, "lh">; 50defm LW : LAQ_r_aq_rl<0b010, "lw">; 51defm SB : SRL_r_aq_rl<0b000, "sb">; 52defm SH : SRL_r_aq_rl<0b001, "sh">; 53defm SW : SRL_r_aq_rl<0b010, "sw">; 54} // Predicates = [HasStdExtZalasr] 55 56let Predicates = [HasStdExtZalasr, IsRV64] in { 57defm LD : LAQ_r_aq_rl<0b011, "ld">; 58defm SD : SRL_r_aq_rl<0b011, "sd">; 59} // Predicates = [HasStdExtZalasr, IsRV64] 60