1//===-- RISCVInstrInfoZa.td - RISC-V Atomic instructions ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard atomic 'Za*' 10// extensions: 11// - Zawrs (v1.0) : Wait-on-Reservation-Set. 12// - Zacas (v1.0-rc1) : Atomic Compare-and-Swap. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// Zacas (Atomic Compare-and-Swap) 18//===----------------------------------------------------------------------===// 19 20let Predicates = [HasStdExtZacas] in { 21defm AMOCAS_W : AMO_rr_aq_rl<0b00101, 0b010, "amocas.w">; 22defm AMOCAS_D : AMO_rr_aq_rl<0b00101, 0b011, "amocas.d">; 23} // Predicates = [HasStdExtZacas] 24 25let Predicates = [HasStdExtZacas, IsRV64] in { 26defm AMOCAS_Q : AMO_rr_aq_rl<0b00101, 0b100, "amocas.q">; 27} // Predicates = [HasStdExtZacas, IsRV64] 28 29//===----------------------------------------------------------------------===// 30// Zawrs (Wait-on-Reservation-Set) 31//===----------------------------------------------------------------------===// 32 33let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 34class WRSInst<bits<12> funct12, string opcodestr> 35 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, ""> { 36 let rs1 = 0; 37 let rd = 0; 38 let imm12 = funct12; 39} 40 41let Predicates = [HasStdExtZawrs] in { 42def WRS_NTO : WRSInst<0b000000001101, "wrs.nto">, Sched<[]>; 43def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>; 44} // Predicates = [HasStdExtZawrs] 45