1//===-- RISCVInstrInfoXVentana.td --------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the vendor extensions defined by Ventana Micro Systems. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// XVentanaCondOps 15//===----------------------------------------------------------------------===// 16 17let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0, 18 mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "XVentana" in 19class VTMaskedMove<bits<3> funct3, string opcodestr> 20 : RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd), 21 (ins GPR:$rs1, GPR:$rs2), opcodestr, 22 "$rd, $rs1, $rs2"> { 23} 24 25def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">, 26 Sched<[WriteIALU, ReadIALU, ReadIALU]>; 27 28def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">, 29 Sched<[WriteIALU, ReadIALU, ReadIALU]>; 30 31let Predicates = [IsRV64, HasVendorXVentanaCondOps] in { 32def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, GPR:$rc)), 33 (VT_MASKC GPR:$rs1, GPR:$rc)>; 34def : Pat<(i64 (riscv_czero_nez GPR:$rs1, GPR:$rc)), 35 (VT_MASKCN GPR:$rs1, GPR:$rc)>; 36 37def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, (riscv_setne (i64 GPR:$rc)))), 38 (VT_MASKC GPR:$rs1, GPR:$rc)>; 39def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, (riscv_seteq (i64 GPR:$rc)))), 40 (VT_MASKCN GPR:$rs1, GPR:$rc)>; 41def : Pat<(i64 (riscv_czero_nez GPR:$rs1, (riscv_setne (i64 GPR:$rc)))), 42 (VT_MASKCN GPR:$rs1, GPR:$rc)>; 43def : Pat<(i64 (riscv_czero_nez GPR:$rs1, (riscv_seteq (i64 GPR:$rc)))), 44 (VT_MASKC GPR:$rs1, GPR:$rc)>; 45} // Predicates = [IsRV64, HasVendorXVentanaCondOps] 46