xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td (revision 9f23cbd6cae82fd77edfad7173432fa8dccd0a95) 
1//===-- RISCVInstrInfoXTHead.td ----------------------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the vendor extensions defined by T-Head of Alibaba.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Instruction class templates
15//===----------------------------------------------------------------------===//
16class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
17                   string opcodestr, string argstr>
18    : RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> {
19  let Inst{26} = 0;
20  let Opcode = OPC_CUSTOM_0.Value;
21  let DecoderNamespace = "THeadV";
22}
23
24class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
25                   string opcodestr, string argstr>
26    : RVInstVX<funct6, opv, outs, ins, opcodestr, argstr> {
27  let Inst{26} = 1;
28  let Opcode = OPC_CUSTOM_0.Value;
29  let DecoderNamespace = "THeadV";
30}
31
32let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
33// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
34class THVdotALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
35    : THInstVdotVV<funct6, opv, (outs VR:$vd),
36                   (ins VR:$vs1, VR:$vs2, VMaskOp:$vm),
37                   opcodestr, "$vd, $vs1, $vs2$vm">;
38
39// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
40class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
41    : THInstVdotVX<funct6, opv, (outs VR:$vd),
42                   (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm),
43                   opcodestr, "$vd, $rs1, $vs2$vm">;
44} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
45
46//===----------------------------------------------------------------------===//
47// Combination of instruction classes.
48// Use these multiclasses to define instructions more easily.
49//===----------------------------------------------------------------------===//
50multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> {
51  def _VX : THVdotALUrVX<funct6, OPMVX, opcodestr # ".vx">;
52}
53
54multiclass THVdotVMAQA<string opcodestr, bits<6> funct6> {
55  def _VV   : THVdotALUrVV<funct6, OPMVX, opcodestr # ".vv">;
56  defm ""   : THVdotVMAQA_VX<opcodestr, funct6>;
57}
58
59//===----------------------------------------------------------------------===//
60// Instructions
61//===----------------------------------------------------------------------===//
62let Predicates = [HasVendorXTHeadVdot],
63    Constraints = "@earlyclobber $vd",
64    RVVConstraint = WidenV in {
65defm THVdotVMAQA      : THVdotVMAQA<"th.vmaqa",     0b100000>;
66defm THVdotVMAQAU     : THVdotVMAQA<"th.vmaqau",    0b100010>;
67defm THVdotVMAQASU    : THVdotVMAQA<"th.vmaqasu",   0b100100>;
68defm THVdotVMAQAUS    : THVdotVMAQA_VX<"th.vmaqaus",0b100110>;
69}
70
71// Associate LMUL with tablegen records of register classes.
72def THVdotV_M1  : LMULInfo<0b000,  8,   VR, VR,   VR,   VR,   VR, "M1">;
73def THVdotV_M2  : LMULInfo<0b001, 16, VRM2, VRM2, VR,   VR,   VR, "M2">;
74def THVdotV_M4  : LMULInfo<0b010, 32, VRM4, VRM4, VRM2, VR,   VR, "M4">;
75def THVdotV_M8  : LMULInfo<0b011, 64, VRM8, VRM8, VRM4, VRM2, VR, "M8">;
76
77defvar MxListTHVdot = [V_MF2, THVdotV_M1, THVdotV_M2, THVdotV_M4, THVdotV_M8];
78
79defset list<VTypeInfoToWide> AllQuadWidenableInt8NoVLMulVectors = {
80  def : VTypeInfoToWide<VI8MF2,  VI32MF2>;
81  def : VTypeInfoToWide<VI8M1,   VI32M1>;
82  def : VTypeInfoToWide<VI8M2,   VI32M2>;
83  def : VTypeInfoToWide<VI8M4,   VI32M4>;
84  def : VTypeInfoToWide<VI8M8,   VI32M8>;
85}
86
87//===----------------------------------------------------------------------===//
88// Combination of instruction classes.
89// Use these multiclasses to define instructions more easily.
90//===----------------------------------------------------------------------===//
91multiclass VPseudoVMAQA_VV_VX {
92  foreach m = MxListTHVdot in {
93    defm "" : VPseudoTernaryW_VV<m>;
94    defm "" : VPseudoTernaryW_VX<m>;
95  }
96}
97
98multiclass VPseudoVMAQA_VX {
99  foreach m = MxListTHVdot in {
100    defm "" : VPseudoTernaryW_VX<m>;
101  }
102}
103
104multiclass VPatTernaryVMAQA_VV<string intrinsic, string instruction,
105                               list<VTypeInfoToWide> vtilist> {
106  foreach vtiToWti = vtilist in {
107    defvar vti = vtiToWti.Vti;
108    defvar wti = vtiToWti.Wti;
109    defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
110                                 wti.Vector, vti.Vector, vti.Vector,
111                                 vti.Mask, wti.Log2SEW, vti.LMul,
112                                 wti.RegClass, vti.RegClass, vti.RegClass>;
113  }
114}
115
116multiclass VPatTernaryVMAQA_VX<string intrinsic, string instruction,
117                               list<VTypeInfoToWide> vtilist> {
118  foreach vtiToWti = vtilist in {
119    defvar vti = vtiToWti.Vti;
120    defvar wti = vtiToWti.Wti;
121    defm : VPatTernaryWithPolicy<intrinsic, instruction,
122                                 "V"#vti.ScalarSuffix,
123                                 wti.Vector, vti.Scalar, vti.Vector,
124                                 vti.Mask, wti.Log2SEW, vti.LMul,
125                                 wti.RegClass, vti.ScalarRegClass, vti.RegClass>;
126  }
127}
128
129multiclass VPatTernaryVMAQA_VV_VX<string intrinsic, string instruction,
130                                  list<VTypeInfoToWide> vtilist>
131    : VPatTernaryVMAQA_VV<intrinsic, instruction, vtilist>,
132      VPatTernaryVMAQA_VX<intrinsic, instruction, vtilist>;
133
134//===----------------------------------------------------------------------===//
135// Pseudo-instructions and codegen patterns
136//===----------------------------------------------------------------------===//
137defm PseudoTHVdotVMAQA      : VPseudoVMAQA_VV_VX;
138defm PseudoTHVdotVMAQAU     : VPseudoVMAQA_VV_VX;
139defm PseudoTHVdotVMAQASU    : VPseudoVMAQA_VV_VX;
140defm PseudoTHVdotVMAQAUS    : VPseudoVMAQA_VX;
141
142let Predicates = [HasVendorXTHeadVdot] in {
143defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa",  "PseudoTHVdotVMAQA",  AllQuadWidenableInt8NoVLMulVectors>;
144defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTHVdotVMAQAU", AllQuadWidenableInt8NoVLMulVectors>;
145defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTHVdotVMAQASU",AllQuadWidenableInt8NoVLMulVectors>;
146defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus",   "PseudoTHVdotVMAQAUS",AllQuadWidenableInt8NoVLMulVectors>;
147}
148