1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// 0.10. This version is still experimental as the 'V' extension hasn't been 12/// ratified yet. 13/// 14/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 15/// 16/// Note: the patterns for RVV intrinsics are found in 17/// RISCVInstrInfoVPseudos.td. 18/// 19//===----------------------------------------------------------------------===// 20 21//===----------------------------------------------------------------------===// 22// Helpers to define the VL patterns. 23//===----------------------------------------------------------------------===// 24 25def SDT_RISCVVLE_VL : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>, 26 SDTCisVT<2, XLenVT>]>; 27def SDT_RISCVVSE_VL : SDTypeProfile<0, 3, [SDTCisVec<0>, SDTCisPtrTy<1>, 28 SDTCisVT<2, XLenVT>]>; 29 30def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 31 SDTCisSameAs<0, 2>, 32 SDTCisVec<0>, SDTCisInt<0>, 33 SDTCVecEltisVT<3, i1>, 34 SDTCisSameNumEltsAs<0, 3>, 35 SDTCisVT<4, XLenVT>]>; 36 37def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<2, i1>, 40 SDTCisSameNumEltsAs<0, 2>, 41 SDTCisVT<3, XLenVT>]>; 42def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 43 SDTCisSameAs<0, 2>, 44 SDTCisVec<0>, SDTCisFP<0>, 45 SDTCVecEltisVT<3, i1>, 46 SDTCisSameNumEltsAs<0, 3>, 47 SDTCisVT<4, XLenVT>]>; 48 49def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 50 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, 51 SDTCisVT<1, XLenVT>, 52 SDTCisVT<2, XLenVT>]>>; 53def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 54 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 55 SDTCisEltOfVec<1, 0>, 56 SDTCisVT<2, XLenVT>]>>; 57def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 59 SDTCisInt<0>, 60 SDTCisVT<2, XLenVT>, 61 SDTCisVT<3, XLenVT>]>>; 62def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 63 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 64 SDTCisFP<0>, 65 SDTCisEltOfVec<2, 0>, 66 SDTCisVT<3, XLenVT>]>>; 67 68def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL, 69 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 70def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL, 71 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 72 73def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 74def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 76def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 77def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 78def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 79def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 80def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 81def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 83def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 84def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 86def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 87def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 88def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 89def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 90def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 91def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 92 93def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL>; 94def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL>; 95def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 96def riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 97 98def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 99def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 100def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 101def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 102def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 103def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 104def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 105def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 106def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>; 107def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>; 108 109def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 110 SDTCisSameAs<0, 2>, 111 SDTCisSameAs<0, 3>, 112 SDTCisVec<0>, SDTCisFP<0>, 113 SDTCVecEltisVT<4, i1>, 114 SDTCisSameNumEltsAs<0, 4>, 115 SDTCisVT<5, XLenVT>]>; 116def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 117 118def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 119 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 120 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 121]>; 122def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 124 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 125]>; 126 127def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 128def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 129def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 130 131def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 132 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 133 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 134]>; 135def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 136 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 137 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 138]>; 139 140def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 141def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 142def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 143def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 144 145def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 146 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 147 SDTCisVec<1>, 148 SDTCisSameNumEltsAs<0, 1>, 149 SDTCisSameAs<1, 2>, 150 SDTCisVT<3, OtherVT>, 151 SDTCisSameAs<0, 4>, 152 SDTCisVT<5, XLenVT>]>>; 153 154def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 155 SDTypeProfile<1, 4, [SDTCisVec<0>, 156 SDTCisSameAs<0, 1>, 157 SDTCisVT<2, XLenVT>, 158 SDTCVecEltisVT<3, i1>, 159 SDTCisSameNumEltsAs<0, 3>, 160 SDTCisVT<4, XLenVT>]>>; 161def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 162 SDTypeProfile<1, 4, [SDTCisVec<0>, 163 SDTCisSameAs<0, 1>, 164 SDTCisInt<2>, 165 SDTCisSameNumEltsAs<0, 2>, 166 SDTCisSameSizeAs<0, 2>, 167 SDTCVecEltisVT<3, i1>, 168 SDTCisSameNumEltsAs<0, 3>, 169 SDTCisVT<4, XLenVT>]>>; 170def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 171 SDTypeProfile<1, 4, [SDTCisVec<0>, 172 SDTCisSameAs<0, 1>, 173 SDTCisInt<2>, 174 SDTCVecEltisVT<2, i16>, 175 SDTCisSameNumEltsAs<0, 2>, 176 SDTCVecEltisVT<3, i1>, 177 SDTCisSameNumEltsAs<0, 3>, 178 SDTCisVT<4, XLenVT>]>>; 179 180def SDT_RISCVSelect_VL : SDTypeProfile<1, 4, [ 181 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>, 182 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisVT<4, XLenVT> 183]>; 184 185def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", SDT_RISCVSelect_VL>; 186def riscv_vp_merge_vl : SDNode<"RISCVISD::VP_MERGE_VL", SDT_RISCVSelect_VL>; 187 188def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 189 SDTCisSameAs<0, 2>, 190 SDTCVecEltisVT<0, i1>, 191 SDTCisVT<3, XLenVT>]>; 192def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 193def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 194def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 195 196def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 197 198def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 199 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 200 201def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL", 202 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 203 SDTCisVec<1>, SDTCisInt<1>, 204 SDTCVecEltisVT<2, i1>, 205 SDTCisSameNumEltsAs<1, 2>, 206 SDTCisVT<3, XLenVT>]>>; 207 208def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 209 SDTCisSameNumEltsAs<0, 1>, 210 SDTCisSameNumEltsAs<1, 2>, 211 SDTCVecEltisVT<2, i1>, 212 SDTCisVT<3, XLenVT>]>; 213def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 214def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 215 216def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 217 SDTypeProfile<1, 3, [SDTCisVec<0>, 218 SDTCisSameNumEltsAs<0, 1>, 219 SDTCisSameNumEltsAs<0, 2>, 220 SDTCVecEltisVT<2, i1>, 221 SDTCisVT<3, XLenVT>]>>; 222 223def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 224 SDTCisSameNumEltsAs<0, 1>, 225 SDTCisSameAs<1, 2>, 226 SDTCisSameNumEltsAs<1, 3>, 227 SDTCVecEltisVT<3, i1>, 228 SDTCisVT<4, XLenVT>]>; 229def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 230def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 231def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>; 232def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 233 234def SDTRVVVecReduce : SDTypeProfile<1, 5, [ 235 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 236 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT> 237]>; 238 239def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 240 (riscv_mul_vl node:$A, node:$B, node:$C, 241 node:$D), [{ 242 return N->hasOneUse(); 243}]>; 244 245def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 246 (riscv_vwmul_vl node:$A, node:$B, node:$C, 247 node:$D), [{ 248 return N->hasOneUse(); 249}]>; 250 251def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 252 (riscv_vwmulu_vl node:$A, node:$B, node:$C, 253 node:$D), [{ 254 return N->hasOneUse(); 255}]>; 256 257foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 258 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 259 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 260 261// Ignore the vl operand. 262def SplatFPOp : PatFrag<(ops node:$op), 263 (riscv_vfmv_v_f_vl node:$op, srcvalue)>; 264 265def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 266def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 267def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 268def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 269 270multiclass VPatBinaryVL_VV<SDNode vop, 271 string instruction_name, 272 ValueType result_type, 273 ValueType op_type, 274 ValueType mask_type, 275 int sew, 276 LMULInfo vlmul, 277 VReg op_reg_class> { 278 def : Pat<(result_type (vop 279 (op_type op_reg_class:$rs1), 280 (op_type op_reg_class:$rs2), 281 (mask_type true_mask), 282 VLOpFrag)), 283 (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX) 284 op_reg_class:$rs1, 285 op_reg_class:$rs2, 286 GPR:$vl, sew)>; 287 def : Pat<(result_type (vop 288 (op_type op_reg_class:$rs1), 289 (op_type op_reg_class:$rs2), 290 (mask_type V0), 291 VLOpFrag)), 292 (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX#"_MASK") 293 (result_type (IMPLICIT_DEF)), 294 op_reg_class:$rs1, 295 op_reg_class:$rs2, 296 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 297} 298 299multiclass VPatBinaryVL_XI<SDNode vop, 300 string instruction_name, 301 string suffix, 302 ValueType result_type, 303 ValueType vop_type, 304 ValueType mask_type, 305 int sew, 306 LMULInfo vlmul, 307 VReg vop_reg_class, 308 ComplexPattern SplatPatKind, 309 DAGOperand xop_kind> { 310 def : Pat<(result_type (vop 311 (vop_type vop_reg_class:$rs1), 312 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))), 313 (mask_type true_mask), 314 VLOpFrag)), 315 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX) 316 vop_reg_class:$rs1, 317 xop_kind:$rs2, 318 GPR:$vl, sew)>; 319 def : Pat<(result_type (vop 320 (vop_type vop_reg_class:$rs1), 321 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))), 322 (mask_type V0), 323 VLOpFrag)), 324 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK") 325 (result_type (IMPLICIT_DEF)), 326 vop_reg_class:$rs1, 327 xop_kind:$rs2, 328 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 329} 330 331multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 332 foreach vti = AllIntegerVectors in { 333 defm : VPatBinaryVL_VV<vop, instruction_name, 334 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 335 vti.LMul, vti.RegClass>; 336 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 337 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 338 vti.LMul, vti.RegClass, SplatPat, GPR>; 339 } 340} 341 342multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 343 Operand ImmType = simm5> 344 : VPatBinaryVL_VV_VX<vop, instruction_name> { 345 foreach vti = AllIntegerVectors in { 346 defm : VPatBinaryVL_XI<vop, instruction_name, "VI", 347 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 348 vti.LMul, vti.RegClass, 349 !cast<ComplexPattern>(SplatPat#_#ImmType), 350 ImmType>; 351 } 352} 353 354multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> { 355 foreach VtiToWti = AllWidenableIntVectors in { 356 defvar vti = VtiToWti.Vti; 357 defvar wti = VtiToWti.Wti; 358 defm : VPatBinaryVL_VV<vop, instruction_name, 359 wti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 360 vti.LMul, vti.RegClass>; 361 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 362 wti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 363 vti.LMul, vti.RegClass, SplatPat, GPR>; 364 } 365} 366 367multiclass VPatBinaryVL_VF<SDNode vop, 368 string instruction_name, 369 ValueType result_type, 370 ValueType vop_type, 371 ValueType mask_type, 372 int sew, 373 LMULInfo vlmul, 374 VReg vop_reg_class, 375 RegisterClass scalar_reg_class> { 376 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 377 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 378 (mask_type true_mask), 379 VLOpFrag)), 380 (!cast<Instruction>(instruction_name#"_"#vlmul.MX) 381 vop_reg_class:$rs1, 382 scalar_reg_class:$rs2, 383 GPR:$vl, sew)>; 384 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 385 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 386 (mask_type V0), 387 VLOpFrag)), 388 (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_MASK") 389 (result_type (IMPLICIT_DEF)), 390 vop_reg_class:$rs1, 391 scalar_reg_class:$rs2, 392 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 393} 394 395multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 396 foreach vti = AllFloatVectors in { 397 defm : VPatBinaryVL_VV<vop, instruction_name, 398 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 399 vti.LMul, vti.RegClass>; 400 defm : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 401 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 402 vti.LMul, vti.RegClass, vti.ScalarRegClass>; 403 } 404} 405 406multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 407 foreach fvti = AllFloatVectors in { 408 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 409 fvti.RegClass:$rs1, 410 (fvti.Mask true_mask), 411 VLOpFrag)), 412 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 413 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 414 GPR:$vl, fvti.Log2SEW)>; 415 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 416 fvti.RegClass:$rs1, 417 (fvti.Mask V0), 418 VLOpFrag)), 419 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 420 (fvti.Vector (IMPLICIT_DEF)), 421 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 422 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 423 } 424} 425 426multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 427 CondCode cc> { 428 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 429 vti.RegClass:$rs2, cc, 430 (vti.Mask true_mask), 431 VLOpFrag)), 432 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 433 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 434 vti.Log2SEW)>; 435} 436 437// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 438multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 439 CondCode cc, CondCode invcc> : 440 VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 441 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 442 vti.RegClass:$rs1, invcc, 443 (vti.Mask true_mask), 444 VLOpFrag)), 445 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 446 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 447 vti.Log2SEW)>; 448} 449 450multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 451 CondCode cc, CondCode invcc> { 452 defvar instruction = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX); 453 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 454 (SplatPat (XLenVT GPR:$rs2)), cc, 455 (vti.Mask true_mask), 456 VLOpFrag)), 457 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 458 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 459 (vti.Vector vti.RegClass:$rs1), invcc, 460 (vti.Mask true_mask), 461 VLOpFrag)), 462 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 463} 464 465multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 466 CondCode cc, CondCode invcc> { 467 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 468 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 469 (SplatPat_simm5 simm5:$rs2), cc, 470 (vti.Mask true_mask), 471 VLOpFrag)), 472 (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.Log2SEW)>; 473 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 474 (vti.Vector vti.RegClass:$rs1), invcc, 475 (vti.Mask true_mask), 476 VLOpFrag)), 477 (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>; 478} 479 480multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name, 481 CondCode cc, ComplexPattern splatpat_kind> { 482 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 483 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 484 (splatpat_kind simm5:$rs2), cc, 485 (vti.Mask true_mask), 486 VLOpFrag)), 487 (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2), 488 GPR:$vl, vti.Log2SEW)>; 489} 490 491multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 492 string inst_name, 493 string swapped_op_inst_name> { 494 foreach fvti = AllFloatVectors in { 495 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 496 fvti.RegClass:$rs2, 497 cc, 498 (fvti.Mask true_mask), 499 VLOpFrag)), 500 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX) 501 fvti.RegClass:$rs1, fvti.RegClass:$rs2, GPR:$vl, fvti.Log2SEW)>; 502 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 503 (SplatFPOp fvti.ScalarRegClass:$rs2), 504 cc, 505 (fvti.Mask true_mask), 506 VLOpFrag)), 507 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 508 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 509 GPR:$vl, fvti.Log2SEW)>; 510 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 511 (fvti.Vector fvti.RegClass:$rs1), 512 cc, 513 (fvti.Mask true_mask), 514 VLOpFrag)), 515 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 516 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 517 GPR:$vl, fvti.Log2SEW)>; 518 } 519} 520 521multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 522 list <VTypeInfoToFraction> fraction_list> { 523 foreach vtiTofti = fraction_list in { 524 defvar vti = vtiTofti.Vti; 525 defvar fti = vtiTofti.Fti; 526 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 527 true_mask, VLOpFrag)), 528 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX) 529 fti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 530 } 531} 532 533multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 534 foreach fvti = AllFloatVectors in { 535 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 536 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 537 (fvti.Mask true_mask), 538 VLOpFrag)), 539 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 540 fvti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>; 541 } 542} 543 544multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 545 foreach fvti = AllFloatVectors in { 546 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 547 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 548 (ivti.Mask true_mask), 549 VLOpFrag)), 550 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 551 ivti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 552 } 553} 554 555multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 556 foreach fvtiToFWti = AllWidenableFloatVectors in { 557 defvar fvti = fvtiToFWti.Vti; 558 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 559 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 560 (fvti.Mask true_mask), 561 VLOpFrag)), 562 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 563 fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 564 } 565} 566 567multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 568 foreach vtiToWti = AllWidenableIntToFloatVectors in { 569 defvar ivti = vtiToWti.Vti; 570 defvar fwti = vtiToWti.Wti; 571 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 572 (ivti.Mask true_mask), 573 VLOpFrag)), 574 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 575 ivti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>; 576 } 577} 578 579multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 580 foreach vtiToWti = AllWidenableIntToFloatVectors in { 581 defvar vti = vtiToWti.Vti; 582 defvar fwti = vtiToWti.Wti; 583 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 584 (fwti.Mask true_mask), 585 VLOpFrag)), 586 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX) 587 fwti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 588 } 589} 590 591multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 592 foreach fvtiToFWti = AllWidenableFloatVectors in { 593 defvar fvti = fvtiToFWti.Vti; 594 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 595 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 596 (iwti.Mask true_mask), 597 VLOpFrag)), 598 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 599 iwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 600 } 601} 602 603multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 604 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 605 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 606 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 607 (vti.Mask true_mask), 608 VLOpFrag)), 609 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 610 (vti_m1.Vector VR:$merge), 611 (vti.Vector vti.RegClass:$rs1), 612 (vti_m1.Vector VR:$rs2), 613 GPR:$vl, vti.Log2SEW)>; 614 615 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 616 (vti.Mask V0), VLOpFrag)), 617 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 618 (vti_m1.Vector VR:$merge), 619 (vti.Vector vti.RegClass:$rs1), 620 (vti_m1.Vector VR:$rs2), 621 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 622 } 623} 624 625multiclass VPatBinarySDNodeExt_V_WV<SDNode op, PatFrags extop, string instruction_name> { 626 foreach vti = AllWidenableIntVectors in { 627 def : Pat< 628 (vti.Vti.Vector 629 (riscv_trunc_vector_vl 630 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 631 (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), 632 (riscv_vmset_vl VLMax), 633 VLMax)), 634 (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX) 635 vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1, 636 vti.Vti.AVL, vti.Vti.Log2SEW)>; 637 } 638} 639 640multiclass VPatBinarySDNodeExt_V_WX<SDNode op, PatFrags extop, string instruction_name> { 641 foreach vti = AllWidenableIntVectors in { 642 def : Pat< 643 (vti.Vti.Vector 644 (riscv_trunc_vector_vl 645 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 646 (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))), 647 (riscv_vmset_vl VLMax), 648 VLMax)), 649 (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) 650 vti.Wti.RegClass:$rs2, GPR:$rs1, 651 vti.Vti.AVL, vti.Vti.Log2SEW)>; 652 } 653} 654 655 656multiclass VPatBinarySDNode_V_WV<SDNode op, string instruction_name> { 657 defm : VPatBinarySDNodeExt_V_WV<op, sext_oneuse, instruction_name>; 658 defm : VPatBinarySDNodeExt_V_WV<op, zext_oneuse, instruction_name>; 659} 660 661multiclass VPatBinarySDNode_V_WX<SDNode op, string instruction_name> { 662 defm : VPatBinarySDNodeExt_V_WX<op, sext_oneuse, instruction_name>; 663 defm : VPatBinarySDNodeExt_V_WX<op, zext_oneuse, instruction_name>; 664} 665 666//===----------------------------------------------------------------------===// 667// Patterns. 668//===----------------------------------------------------------------------===// 669 670let Predicates = [HasVInstructions] in { 671 672// 7.4. Vector Unit-Stride Instructions 673foreach vti = AllVectors in { 674 defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX); 675 defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX); 676 // Load 677 def : Pat<(vti.Vector (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)), 678 (load_instr BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>; 679 // Store 680 def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), BaseAddr:$rs1, 681 VLOpFrag), 682 (store_instr vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>; 683} 684 685foreach mti = AllMasks in { 686 defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#mti.BX); 687 defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#mti.BX); 688 def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)), 689 (load_instr BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>; 690 def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1, 691 VLOpFrag), 692 (store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>; 693} 694 695// 12.1. Vector Single-Width Integer Add and Subtract 696defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 697defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 698// Handle VRSUB specially since it's the only integer binary op with reversed 699// pattern operands 700foreach vti = AllIntegerVectors in { 701 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 702 (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), 703 VLOpFrag), 704 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX) 705 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 706 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 707 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 708 VLOpFrag), 709 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 710 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, 711 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 712 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 713 (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), 714 VLOpFrag), 715 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX) 716 vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>; 717 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 718 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 719 VLOpFrag), 720 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 721 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2, 722 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 723} 724 725// 12.2. Vector Widening Integer Add/Subtract 726defm : VPatBinaryWVL_VV_VX<riscv_vwaddu_vl, "PseudoVWADDU">; 727 728// 12.3. Vector Integer Extension 729defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 730 AllFractionableVF2IntVectors>; 731defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 732 AllFractionableVF2IntVectors>; 733defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 734 AllFractionableVF4IntVectors>; 735defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 736 AllFractionableVF4IntVectors>; 737defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 738 AllFractionableVF8IntVectors>; 739defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 740 AllFractionableVF8IntVectors>; 741 742// 12.5. Vector Bitwise Logical Instructions 743defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 744defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 745defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 746 747// 12.6. Vector Single-Width Bit Shift Instructions 748defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 749defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 750defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 751 752foreach vti = AllIntegerVectors in { 753 // Emit shift by 1 as an add since it might be faster. 754 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 755 (riscv_vmv_v_x_vl 1, (XLenVT srcvalue)), 756 (vti.Mask true_mask), 757 VLOpFrag), 758 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 759 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 760} 761 762// 12.7. Vector Narrowing Integer Right Shift Instructions 763defm : VPatBinarySDNode_V_WV<srl, "PseudoVNSRL">; 764defm : VPatBinarySDNode_V_WX<srl, "PseudoVNSRL">; 765defm : VPatBinarySDNode_V_WV<sra, "PseudoVNSRA">; 766defm : VPatBinarySDNode_V_WX<sra, "PseudoVNSRA">; 767 768foreach vtiTowti = AllWidenableIntVectors in { 769 defvar vti = vtiTowti.Vti; 770 defvar wti = vtiTowti.Wti; 771 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 772 (vti.Mask true_mask), 773 VLOpFrag)), 774 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 775 wti.RegClass:$rs1, X0, GPR:$vl, vti.Log2SEW)>; 776 777 def : Pat<(vti.Vector 778 (riscv_trunc_vector_vl 779 (wti.Vector 780 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 781 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 782 (!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX) 783 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 784 def : Pat<(vti.Vector 785 (riscv_trunc_vector_vl 786 (wti.Vector 787 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 788 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 789 (!cast<Instruction>("PseudoVNSRA_WI_"#vti.LMul.MX) 790 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 791 792 def : Pat<(vti.Vector 793 (riscv_trunc_vector_vl 794 (wti.Vector 795 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 796 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 797 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 798 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 799 def : Pat<(vti.Vector 800 (riscv_trunc_vector_vl 801 (wti.Vector 802 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 803 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 804 (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX) 805 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 806} 807 808// 12.8. Vector Integer Comparison Instructions 809foreach vti = AllIntegerVectors in { 810 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 811 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 812 813 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 814 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 815 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 816 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 817 818 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 819 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 820 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 821 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 822 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 823 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 824 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 825 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 826 // There is no VMSGE(U)_VX instruction 827 828 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 829 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 830 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 831 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 832 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 833 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 834 835 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT, 836 SplatPat_simm5_plus1_nonzero>; 837 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT, 838 SplatPat_simm5_plus1_nonzero>; 839 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGT", SETGE, 840 SplatPat_simm5_plus1>; 841 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGTU", SETUGE, 842 SplatPat_simm5_plus1_nonzero>; 843} // foreach vti = AllIntegerVectors 844 845// 12.9. Vector Integer Min/Max Instructions 846defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 847defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 848defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 849defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 850 851// 12.10. Vector Single-Width Integer Multiply Instructions 852defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 853defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 854defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 855 856// 12.11. Vector Integer Divide Instructions 857defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 858defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 859defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 860defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 861 862// 12.12. Vector Widening Integer Multiply Instructions 863defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 864defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 865defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; 866 867// 12.13 Vector Single-Width Integer Multiply-Add Instructions 868foreach vti = AllIntegerVectors in { 869 // NOTE: We choose VMADD because it has the most commuting freedom. So it 870 // works best with how TwoAddressInstructionPass tries commuting. 871 defvar suffix = vti.LMul.MX; 872 def : Pat<(vti.Vector 873 (riscv_add_vl vti.RegClass:$rs2, 874 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 875 vti.RegClass:$rd, 876 (vti.Mask true_mask), VLOpFrag), 877 (vti.Mask true_mask), VLOpFrag)), 878 (!cast<Instruction>("PseudoVMADD_VV_"# suffix) 879 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 880 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 881 def : Pat<(vti.Vector 882 (riscv_sub_vl vti.RegClass:$rs2, 883 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 884 vti.RegClass:$rd, 885 (vti.Mask true_mask), VLOpFrag), 886 (vti.Mask true_mask), VLOpFrag)), 887 (!cast<Instruction>("PseudoVNMSUB_VV_"# suffix) 888 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 889 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 890 891 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 892 // commutable. 893 def : Pat<(vti.Vector 894 (riscv_add_vl vti.RegClass:$rs2, 895 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 896 vti.RegClass:$rd, 897 (vti.Mask true_mask), VLOpFrag), 898 (vti.Mask true_mask), VLOpFrag)), 899 (!cast<Instruction>("PseudoVMADD_VX_" # suffix) 900 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 901 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 902 def : Pat<(vti.Vector 903 (riscv_sub_vl vti.RegClass:$rs2, 904 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 905 vti.RegClass:$rd, 906 (vti.Mask true_mask), 907 VLOpFrag), 908 (vti.Mask true_mask), VLOpFrag)), 909 (!cast<Instruction>("PseudoVNMSUB_VX_" # suffix) 910 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 911 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 912} 913 914// 12.14. Vector Widening Integer Multiply-Add Instructions 915foreach vtiTowti = AllWidenableIntVectors in { 916 defvar vti = vtiTowti.Vti; 917 defvar wti = vtiTowti.Wti; 918 def : Pat<(wti.Vector 919 (riscv_add_vl wti.RegClass:$rd, 920 (riscv_vwmul_vl_oneuse vti.RegClass:$rs1, 921 (vti.Vector vti.RegClass:$rs2), 922 (vti.Mask true_mask), VLOpFrag), 923 (vti.Mask true_mask), VLOpFrag)), 924 (!cast<Instruction>("PseudoVWMACC_VV_" # vti.LMul.MX) 925 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 926 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 927 def : Pat<(wti.Vector 928 (riscv_add_vl wti.RegClass:$rd, 929 (riscv_vwmulu_vl_oneuse vti.RegClass:$rs1, 930 (vti.Vector vti.RegClass:$rs2), 931 (vti.Mask true_mask), VLOpFrag), 932 (vti.Mask true_mask), VLOpFrag)), 933 (!cast<Instruction>("PseudoVWMACCU_VV_" # vti.LMul.MX) 934 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 935 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 936 937 def : Pat<(wti.Vector 938 (riscv_add_vl wti.RegClass:$rd, 939 (riscv_vwmul_vl_oneuse (SplatPat XLenVT:$rs1), 940 (vti.Vector vti.RegClass:$rs2), 941 (vti.Mask true_mask), VLOpFrag), 942 (vti.Mask true_mask), VLOpFrag)), 943 (!cast<Instruction>("PseudoVWMACC_VX_" # vti.LMul.MX) 944 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 945 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 946 def : Pat<(wti.Vector 947 (riscv_add_vl wti.RegClass:$rd, 948 (riscv_vwmulu_vl_oneuse (SplatPat XLenVT:$rs1), 949 (vti.Vector vti.RegClass:$rs2), 950 (vti.Mask true_mask), VLOpFrag), 951 (vti.Mask true_mask), VLOpFrag)), 952 (!cast<Instruction>("PseudoVWMACCU_VX_" # vti.LMul.MX) 953 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 954 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 955} 956 957// 12.15. Vector Integer Merge Instructions 958foreach vti = AllIntegerVectors in { 959 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 960 vti.RegClass:$rs1, 961 vti.RegClass:$rs2, 962 VLOpFrag)), 963 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 964 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), 965 GPR:$vl, vti.Log2SEW)>; 966 967 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 968 (SplatPat XLenVT:$rs1), 969 vti.RegClass:$rs2, 970 VLOpFrag)), 971 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 972 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 973 974 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 975 (SplatPat_simm5 simm5:$rs1), 976 vti.RegClass:$rs2, 977 VLOpFrag)), 978 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 979 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 980 981 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 982 vti.RegClass:$rs1, 983 vti.RegClass:$rs2, 984 VLOpFrag)), 985 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX#"_TU") 986 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1, 987 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 988 989 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 990 (SplatPat XLenVT:$rs1), 991 vti.RegClass:$rs2, 992 VLOpFrag)), 993 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX#"_TU") 994 vti.RegClass:$rs2, vti.RegClass:$rs2, GPR:$rs1, 995 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 996 997 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 998 (SplatPat_simm5 simm5:$rs1), 999 vti.RegClass:$rs2, 1000 VLOpFrag)), 1001 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU") 1002 vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, 1003 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1004} 1005 1006// 12.16. Vector Integer Move Instructions 1007foreach vti = AllIntegerVectors in { 1008 def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, VLOpFrag)), 1009 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 1010 $rs2, GPR:$vl, vti.Log2SEW)>; 1011 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 1012 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (ImmPat XLenVT:$imm5), 1013 VLOpFrag)), 1014 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 1015 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1016} 1017 1018// 12.1. Vector Single-Width Saturating Add and Subtract 1019defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 1020defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 1021defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 1022defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 1023 1024} // Predicates = [HasVInstructions] 1025 1026// 15.1. Vector Single-Width Integer Reduction Instructions 1027let Predicates = [HasVInstructions] in { 1028defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 1029defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 1030defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 1031defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 1032defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 1033defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 1034defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 1035defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 1036} // Predicates = [HasVInstructions] 1037 1038// 15.3. Vector Single-Width Floating-Point Reduction Instructions 1039let Predicates = [HasVInstructionsAnyF] in { 1040defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 1041defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>; 1042defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>; 1043defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>; 1044} // Predicates = [HasVInstructionsAnyF] 1045 1046let Predicates = [HasVInstructionsAnyF] in { 1047 1048// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 1049defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 1050defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 1051defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 1052 1053// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 1054defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 1055defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 1056defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 1057 1058// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 1059foreach vti = AllFloatVectors in { 1060 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 1061 // works best with how TwoAddressInstructionPass tries commuting. 1062 defvar suffix = vti.LMul.MX; 1063 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1064 vti.RegClass:$rs2, (vti.Mask true_mask), 1065 VLOpFrag)), 1066 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 1067 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1068 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1069 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1070 (riscv_fneg_vl vti.RegClass:$rs2, 1071 (vti.Mask true_mask), 1072 VLOpFrag), 1073 (vti.Mask true_mask), 1074 VLOpFrag)), 1075 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 1076 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1077 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1078 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1079 (vti.Mask true_mask), 1080 VLOpFrag), 1081 vti.RegClass:$rd, 1082 (riscv_fneg_vl vti.RegClass:$rs2, 1083 (vti.Mask true_mask), 1084 VLOpFrag), 1085 (vti.Mask true_mask), 1086 VLOpFrag)), 1087 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 1088 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1089 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1090 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1091 (vti.Mask true_mask), 1092 VLOpFrag), 1093 vti.RegClass:$rd, vti.RegClass:$rs2, 1094 (vti.Mask true_mask), 1095 VLOpFrag)), 1096 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 1097 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1098 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1099 1100 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 1101 // commutable. 1102 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1103 vti.RegClass:$rd, vti.RegClass:$rs2, 1104 (vti.Mask true_mask), 1105 VLOpFrag)), 1106 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 1107 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1108 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1109 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1110 vti.RegClass:$rd, 1111 (riscv_fneg_vl vti.RegClass:$rs2, 1112 (vti.Mask true_mask), 1113 VLOpFrag), 1114 (vti.Mask true_mask), 1115 VLOpFrag)), 1116 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1117 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1118 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1119 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1120 (riscv_fneg_vl vti.RegClass:$rd, 1121 (vti.Mask true_mask), 1122 VLOpFrag), 1123 (riscv_fneg_vl vti.RegClass:$rs2, 1124 (vti.Mask true_mask), 1125 VLOpFrag), 1126 (vti.Mask true_mask), 1127 VLOpFrag)), 1128 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1129 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1130 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1131 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1132 (riscv_fneg_vl vti.RegClass:$rd, 1133 (vti.Mask true_mask), 1134 VLOpFrag), 1135 vti.RegClass:$rs2, 1136 (vti.Mask true_mask), 1137 VLOpFrag)), 1138 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1139 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1140 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1141 1142 // The splat might be negated. 1143 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1144 (vti.Mask true_mask), 1145 VLOpFrag), 1146 vti.RegClass:$rd, 1147 (riscv_fneg_vl vti.RegClass:$rs2, 1148 (vti.Mask true_mask), 1149 VLOpFrag), 1150 (vti.Mask true_mask), 1151 VLOpFrag)), 1152 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1153 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1154 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1155 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1156 (vti.Mask true_mask), 1157 VLOpFrag), 1158 vti.RegClass:$rd, vti.RegClass:$rs2, 1159 (vti.Mask true_mask), 1160 VLOpFrag)), 1161 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1162 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1163 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1164} 1165 1166// 14.11. Vector Floating-Point MIN/MAX Instructions 1167defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; 1168defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; 1169 1170// 14.13. Vector Floating-Point Compare Instructions 1171defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1172defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1173 1174defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 1175defm : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 1176 1177defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 1178defm : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 1179 1180defm : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 1181defm : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 1182 1183foreach vti = AllFloatVectors in { 1184 // 14.8. Vector Floating-Point Square-Root Instruction 1185 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 1186 VLOpFrag), 1187 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 1188 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1189 1190 // 14.12. Vector Floating-Point Sign-Injection Instructions 1191 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1192 VLOpFrag), 1193 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 1194 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1195 // Handle fneg with VFSGNJN using the same input for both operands. 1196 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1197 VLOpFrag), 1198 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1199 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1200 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1201 (vti.Vector vti.RegClass:$rs2), 1202 (vti.Mask true_mask), 1203 VLOpFrag), 1204 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 1205 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1206 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1207 (riscv_fneg_vl vti.RegClass:$rs2, 1208 (vti.Mask true_mask), 1209 VLOpFrag), 1210 (vti.Mask true_mask), 1211 VLOpFrag), 1212 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1213 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1214 1215 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1216 (SplatFPOp vti.ScalarRegClass:$rs2), 1217 (vti.Mask true_mask), 1218 VLOpFrag), 1219 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 1220 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1221} 1222 1223foreach fvti = AllFloatVectors in { 1224 // Floating-point vselects: 1225 // 12.15. Vector Integer Merge Instructions 1226 // 14.15. Vector Floating-Point Merge Instruction 1227 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1228 fvti.RegClass:$rs1, 1229 fvti.RegClass:$rs2, 1230 VLOpFrag)), 1231 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 1232 fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1233 GPR:$vl, fvti.Log2SEW)>; 1234 1235 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1236 (SplatFPOp fvti.ScalarRegClass:$rs1), 1237 fvti.RegClass:$rs2, 1238 VLOpFrag)), 1239 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 1240 fvti.RegClass:$rs2, 1241 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1242 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1243 1244 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1245 (SplatFPOp (fvti.Scalar fpimm0)), 1246 fvti.RegClass:$rs2, 1247 VLOpFrag)), 1248 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 1249 fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1250 1251 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1252 fvti.RegClass:$rs1, 1253 fvti.RegClass:$rs2, 1254 VLOpFrag)), 1255 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX#"_TU") 1256 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1257 GPR:$vl, fvti.Log2SEW)>; 1258 1259 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1260 (SplatFPOp fvti.ScalarRegClass:$rs1), 1261 fvti.RegClass:$rs2, 1262 VLOpFrag)), 1263 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX#"_TU") 1264 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 1265 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1266 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1267 1268 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1269 (SplatFPOp (fvti.Scalar fpimm0)), 1270 fvti.RegClass:$rs2, 1271 VLOpFrag)), 1272 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU") 1273 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), 1274 GPR:$vl, fvti.Log2SEW)>; 1275 1276 // 14.16. Vector Floating-Point Move Instruction 1277 // If we're splatting fpimm0, use vmv.v.x vd, x0. 1278 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1279 (fvti.Scalar (fpimm0)), VLOpFrag)), 1280 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 1281 0, GPR:$vl, fvti.Log2SEW)>; 1282 1283 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1284 (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1285 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1286 fvti.LMul.MX) 1287 (fvti.Scalar fvti.ScalarRegClass:$rs2), 1288 GPR:$vl, fvti.Log2SEW)>; 1289 1290 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 1291 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 1292 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 1293 defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 1294 defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 1295 1296 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 1297 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 1298 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 1299 defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 1300 defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 1301 foreach fvtiToFWti = AllWidenableFloatVectors in { 1302 defvar fvti = fvtiToFWti.Vti; 1303 defvar fwti = fvtiToFWti.Wti; 1304 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 1305 (fvti.Mask true_mask), 1306 VLOpFrag)), 1307 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX) 1308 fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1309 } 1310 1311 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 1312 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 1313 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 1314 defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 1315 defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 1316 foreach fvtiToFWti = AllWidenableFloatVectors in { 1317 defvar fvti = fvtiToFWti.Vti; 1318 defvar fwti = fvtiToFWti.Wti; 1319 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 1320 (fwti.Mask true_mask), 1321 VLOpFrag)), 1322 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX) 1323 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1324 1325 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1326 (fwti.Mask true_mask), 1327 VLOpFrag)), 1328 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX) 1329 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1330 } 1331} 1332 1333} // Predicates = [HasVInstructionsAnyF] 1334 1335let Predicates = [HasVInstructions] in { 1336 1337foreach mti = AllMasks in { 1338 // 16.1 Vector Mask-Register Logical Instructions 1339 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 1340 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1341 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 1342 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1343 1344 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1345 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 1346 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1347 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1348 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 1349 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1350 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1351 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 1352 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1353 1354 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 1355 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1356 VLOpFrag)), 1357 (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX) 1358 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1359 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 1360 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1361 VLOpFrag)), 1362 (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX) 1363 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1364 // XOR is associative so we need 2 patterns for VMXNOR. 1365 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 1366 VLOpFrag), 1367 VR:$rs2, VLOpFrag)), 1368 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1369 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1370 1371 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1372 VLOpFrag), 1373 VLOpFrag)), 1374 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1375 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1376 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1377 VLOpFrag), 1378 VLOpFrag)), 1379 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1380 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1381 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1382 VLOpFrag), 1383 VLOpFrag)), 1384 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1385 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1386 1387 // Match the not idiom to the vmnot.m pseudo. 1388 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 1389 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1390 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 1391 1392 // 16.2 Vector count population in mask vcpop.m 1393 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 1394 VLOpFrag)), 1395 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX) 1396 VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1397 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0), 1398 VLOpFrag)), 1399 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK") 1400 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 1401} 1402 1403} // Predicates = [HasVInstructions] 1404 1405let Predicates = [HasVInstructions] in { 1406// 17.1. Integer Scalar Move Instructions 1407// 17.4. Vector Register Gather Instruction 1408foreach vti = AllIntegerVectors in { 1409 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 1410 vti.ScalarRegClass:$rs1, 1411 VLOpFrag)), 1412 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1413 vti.RegClass:$merge, 1414 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1415 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1416 (vti.Vector vti.RegClass:$rs1), 1417 (vti.Mask true_mask), 1418 VLOpFrag)), 1419 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1420 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1421 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1422 (vti.Mask true_mask), 1423 VLOpFrag)), 1424 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1425 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1426 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1427 (vti.Mask true_mask), 1428 VLOpFrag)), 1429 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1430 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1431 1432 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1433 (riscv_vrgather_vv_vl 1434 vti.RegClass:$rs2, 1435 vti.RegClass:$rs1, 1436 (vti.Mask true_mask), 1437 VLOpFrag), 1438 vti.RegClass:$merge, 1439 VLOpFrag)), 1440 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1441 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1442 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1443 1444 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1445 (riscv_vrgather_vx_vl 1446 vti.RegClass:$rs2, 1447 uimm5:$imm, 1448 (vti.Mask true_mask), 1449 VLOpFrag), 1450 vti.RegClass:$merge, 1451 VLOpFrag)), 1452 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1453 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1454 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1455 1456 // emul = lmul * 16 / sew 1457 defvar vlmul = vti.LMul; 1458 defvar octuple_lmul = vlmul.octuple; 1459 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1460 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1461 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1462 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1463 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1464 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1465 (ivti.Vector ivti.RegClass:$rs1), 1466 (vti.Mask true_mask), 1467 VLOpFrag)), 1468 (!cast<Instruction>(inst) 1469 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1470 1471 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1472 (riscv_vrgatherei16_vv_vl 1473 vti.RegClass:$rs2, 1474 (ivti.Vector ivti.RegClass:$rs1), 1475 (vti.Mask true_mask), 1476 VLOpFrag), 1477 vti.RegClass:$merge, 1478 VLOpFrag)), 1479 (!cast<Instruction>(inst#"_MASK") 1480 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1481 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1482 } 1483} 1484 1485} // Predicates = [HasVInstructions] 1486 1487let Predicates = [HasVInstructionsAnyF] in { 1488 1489// 17.2. Floating-Point Scalar Move Instructions 1490foreach vti = AllFloatVectors in { 1491 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1492 (vti.Scalar (fpimm0)), 1493 VLOpFrag)), 1494 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1495 vti.RegClass:$merge, X0, GPR:$vl, vti.Log2SEW)>; 1496 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1497 vti.ScalarRegClass:$rs1, 1498 VLOpFrag)), 1499 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1500 vti.RegClass:$merge, 1501 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1502 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1503 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1504 (ivti.Vector vti.RegClass:$rs1), 1505 (vti.Mask true_mask), 1506 VLOpFrag)), 1507 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1508 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1509 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1510 (vti.Mask true_mask), 1511 VLOpFrag)), 1512 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1513 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1514 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1515 (vti.Mask true_mask), 1516 VLOpFrag)), 1517 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1518 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1519 1520 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1521 (riscv_vrgather_vv_vl 1522 vti.RegClass:$rs2, 1523 (ivti.Vector vti.RegClass:$rs1), 1524 (vti.Mask true_mask), 1525 VLOpFrag), 1526 vti.RegClass:$merge, 1527 VLOpFrag)), 1528 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1529 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1530 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1531 1532 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1533 (riscv_vrgather_vx_vl 1534 vti.RegClass:$rs2, 1535 uimm5:$imm, 1536 (vti.Mask true_mask), 1537 VLOpFrag), 1538 vti.RegClass:$merge, 1539 VLOpFrag)), 1540 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1541 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1542 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1543 1544 defvar vlmul = vti.LMul; 1545 defvar octuple_lmul = vlmul.octuple; 1546 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1547 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1548 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1549 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1550 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1551 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1552 (ivti.Vector ivti.RegClass:$rs1), 1553 (vti.Mask true_mask), 1554 VLOpFrag)), 1555 (!cast<Instruction>(inst) 1556 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1557 1558 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1559 (riscv_vrgatherei16_vv_vl 1560 vti.RegClass:$rs2, 1561 (ivti.Vector ivti.RegClass:$rs1), 1562 (vti.Mask true_mask), 1563 VLOpFrag), 1564 vti.RegClass:$merge, 1565 VLOpFrag)), 1566 (!cast<Instruction>(inst#"_MASK") 1567 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1568 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1569 } 1570} 1571 1572} // Predicates = [HasVInstructionsAnyF] 1573 1574//===----------------------------------------------------------------------===// 1575// Miscellaneous RISCVISD SDNodes 1576//===----------------------------------------------------------------------===// 1577 1578def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 1579 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 1580 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 1581 1582def SDTRVVSlide : SDTypeProfile<1, 5, [ 1583 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 1584 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 1585]>; 1586def SDTRVVSlide1 : SDTypeProfile<1, 4, [ 1587 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisInt<0>, SDTCisVT<2, XLenVT>, 1588 SDTCVecEltisVT<3, i1>, SDTCisSameNumEltsAs<0, 3>, SDTCisVT<4, XLenVT> 1589]>; 1590 1591def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 1592def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 1593def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 1594def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 1595 1596let Predicates = [HasVInstructions] in { 1597 1598foreach vti = AllIntegerVectors in { 1599 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 1600 VLOpFrag)), 1601 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; 1602 1603 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rs1), 1604 GPR:$rs2, (vti.Mask true_mask), 1605 VLOpFrag)), 1606 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 1607 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1608 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rs1), 1609 GPR:$rs2, (vti.Mask true_mask), 1610 VLOpFrag)), 1611 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX) 1612 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1613} 1614 1615foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 1616 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1617 (vti.Vector vti.RegClass:$rs1), 1618 uimm5:$rs2, (vti.Mask true_mask), 1619 VLOpFrag)), 1620 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 1621 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1622 GPR:$vl, vti.Log2SEW)>; 1623 1624 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1625 (vti.Vector vti.RegClass:$rs1), 1626 GPR:$rs2, (vti.Mask true_mask), 1627 VLOpFrag)), 1628 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 1629 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1630 GPR:$vl, vti.Log2SEW)>; 1631 1632 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1633 (vti.Vector vti.RegClass:$rs1), 1634 uimm5:$rs2, (vti.Mask true_mask), 1635 VLOpFrag)), 1636 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 1637 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1638 GPR:$vl, vti.Log2SEW)>; 1639 1640 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1641 (vti.Vector vti.RegClass:$rs1), 1642 GPR:$rs2, (vti.Mask true_mask), 1643 VLOpFrag)), 1644 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 1645 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1646 GPR:$vl, vti.Log2SEW)>; 1647} 1648 1649} // Predicates = [HasVInstructions] 1650