1//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'F', 10// Single-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVFMV_W_X_RV64 19 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>; 20def SDT_RISCVFMV_X_ANYEXTW_RV64 21 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>; 22 23def riscv_fmv_w_x_rv64 24 : SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>; 25def riscv_fmv_x_anyextw_rv64 26 : SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>; 27 28//===----------------------------------------------------------------------===// 29// Operand and SDNode transformation definitions. 30//===----------------------------------------------------------------------===// 31 32// Floating-point rounding mode 33 34def FRMArg : AsmOperandClass { 35 let Name = "FRMArg"; 36 let RenderMethod = "addFRMArgOperands"; 37 let DiagnosticType = "InvalidFRMArg"; 38} 39 40def frmarg : Operand<XLenVT> { 41 let ParserMatchClass = FRMArg; 42 let PrintMethod = "printFRMArg"; 43 let DecoderMethod = "decodeFRMArg"; 44} 45 46//===----------------------------------------------------------------------===// 47// Instruction class templates 48//===----------------------------------------------------------------------===// 49 50let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 51class FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr> 52 : RVInstR4<0b00, opcode, (outs FPR32:$rd), 53 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3), 54 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 55 56class FPFMASDynFrmAlias<FPFMAS_rrr_frm Inst, string OpcodeStr> 57 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 58 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 59 60let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 61class FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 62 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd), 63 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">; 64 65let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 66class FPALUS_rr_frm<bits<7> funct7, string opcodestr> 67 : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd), 68 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr, 69 "$rd, $rs1, $rs2, $funct3">; 70 71class FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr> 72 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 73 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>; 74 75let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 76class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty, 77 RegisterClass rs1ty, string opcodestr> 78 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1), 79 opcodestr, "$rd, $rs1">; 80 81let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 82class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty, 83 string opcodestr> 84 : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd), 85 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr, 86 "$rd, $rs1, $funct3">; 87 88class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr, 89 RegisterClass rdty, RegisterClass rs1ty> 90 : InstAlias<OpcodeStr#" $rd, $rs1", 91 (Inst rdty:$rd, rs1ty:$rs1, 0b111)>; 92 93let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 94class FPCmpS_rr<bits<3> funct3, string opcodestr> 95 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd), 96 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">, 97 Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>; 98 99//===----------------------------------------------------------------------===// 100// Instructions 101//===----------------------------------------------------------------------===// 102 103let Predicates = [HasStdExtF] in { 104let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 105def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd), 106 (ins GPR:$rs1, simm12:$imm12), 107 "flw", "$rd, ${imm12}(${rs1})">, 108 Sched<[WriteFLD32, ReadFMemBase]>; 109 110// Operands for stores are in the order srcreg, base, offset rather than 111// reflecting the order these fields are specified in the instruction 112// encoding. 113let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 114def FSW : RVInstS<0b010, OPC_STORE_FP, (outs), 115 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12), 116 "fsw", "$rs2, ${imm12}(${rs1})">, 117 Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>; 118 119def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">, 120 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>; 121def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">; 122def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">, 123 Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>; 124def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">; 125def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">, 126 Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>; 127def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">; 128def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">, 129 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>; 130def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">; 131 132def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">, 133 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 134def : FPALUSDynFrmAlias<FADD_S, "fadd.s">; 135def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">, 136 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 137def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">; 138def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">, 139 Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>; 140def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">; 141def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">, 142 Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>; 143def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">; 144 145def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">, 146 Sched<[WriteFSqrt32, ReadFSqrt32]> { 147 let rs2 = 0b00000; 148} 149def : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>; 150 151def FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">, 152 Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 153def FSGNJN_S : FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">, 154 Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 155def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">, 156 Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 157def FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">, 158 Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>; 159def FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">, 160 Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>; 161 162def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">, 163 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { 164 let rs2 = 0b00000; 165} 166def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>; 167 168def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">, 169 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { 170 let rs2 = 0b00001; 171} 172def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>; 173 174def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">, 175 Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> { 176 let rs2 = 0b00000; 177} 178 179def FEQ_S : FPCmpS_rr<0b010, "feq.s">; 180def FLT_S : FPCmpS_rr<0b001, "flt.s">; 181def FLE_S : FPCmpS_rr<0b000, "fle.s">; 182 183def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">, 184 Sched<[WriteFClass32, ReadFClass32]> { 185 let rs2 = 0b00000; 186} 187 188def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">, 189 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { 190 let rs2 = 0b00000; 191} 192def : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>; 193 194def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu">, 195 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { 196 let rs2 = 0b00001; 197} 198def : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>; 199 200def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x">, 201 Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]> { 202 let rs2 = 0b00000; 203} 204} // Predicates = [HasStdExtF] 205 206let Predicates = [HasStdExtF, IsRV64] in { 207def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s">, 208 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { 209 let rs2 = 0b00010; 210} 211def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>; 212 213def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s">, 214 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { 215 let rs2 = 0b00011; 216} 217def : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>; 218 219def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l">, 220 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { 221 let rs2 = 0b00010; 222} 223def : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>; 224 225def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu">, 226 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { 227 let rs2 = 0b00011; 228} 229def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>; 230} // Predicates = [HasStdExtF, IsRV64] 231 232//===----------------------------------------------------------------------===// 233// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 234//===----------------------------------------------------------------------===// 235 236let Predicates = [HasStdExtF] in { 237def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>; 238def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>; 239 240def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 241def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 242def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 243 244// fgt.s/fge.s are recognised by the GNU assembler but the canonical 245// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. 246def : InstAlias<"fgt.s $rd, $rs, $rt", 247 (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 248def : InstAlias<"fge.s $rd, $rs, $rt", 249 (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 250 251// The following csr instructions actually alias instructions from the base ISA. 252// However, it only makes sense to support them when the F extension is enabled. 253// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr". 254def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 2>; 255def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs)>; 256def : InstAlias<"fscsr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 2>; 257 258// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them 259// zero weight. 260def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 0>; 261def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs), 0>; 262def : InstAlias<"fssr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 0>; 263 264def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, FRM.Encoding, X0), 2>; 265def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, FRM.Encoding, GPR:$rs)>; 266def : InstAlias<"fsrm $rs", (CSRRW X0, FRM.Encoding, GPR:$rs), 2>; 267def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, FRM.Encoding, uimm5:$imm)>; 268def : InstAlias<"fsrmi $imm", (CSRRWI X0, FRM.Encoding, uimm5:$imm), 2>; 269 270def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, FFLAGS.Encoding, X0), 2>; 271def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, FFLAGS.Encoding, GPR:$rs)>; 272def : InstAlias<"fsflags $rs", (CSRRW X0, FFLAGS.Encoding, GPR:$rs), 2>; 273def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, FFLAGS.Encoding, uimm5:$imm)>; 274def : InstAlias<"fsflagsi $imm", (CSRRWI X0, FFLAGS.Encoding, uimm5:$imm), 2>; 275 276// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both 277// spellings should be supported by standard tools. 278def : MnemonicAlias<"fmv.s.x", "fmv.w.x">; 279def : MnemonicAlias<"fmv.x.s", "fmv.x.w">; 280 281def PseudoFLW : PseudoFloatLoad<"flw", FPR32>; 282def PseudoFSW : PseudoStore<"fsw", FPR32>; 283} // Predicates = [HasStdExtF] 284 285//===----------------------------------------------------------------------===// 286// Pseudo-instructions and codegen patterns 287//===----------------------------------------------------------------------===// 288 289/// Floating point constants 290def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 291 292/// Generic pattern classes 293class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst> 294 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>; 295 296class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 297 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>; 298 299let Predicates = [HasStdExtF] in { 300 301/// Float constants 302def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>; 303 304/// Float conversion operations 305 306// Moves (no conversion) 307def : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>; 308def : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>; 309 310// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 311// are defined later. 312 313/// Float arithmetic operations 314 315def : PatFpr32Fpr32DynFrm<fadd, FADD_S>; 316def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>; 317def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>; 318def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>; 319 320def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; 321 322def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; 323def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; 324 325def : PatFpr32Fpr32<fcopysign, FSGNJ_S>; 326def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; 327 328// fmadd: rs1 * rs2 + rs3 329def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3), 330 (FMADD_S $rs1, $rs2, $rs3, 0b111)>; 331 332// fmsub: rs1 * rs2 - rs3 333def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), 334 (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 335 336// fnmsub: -rs1 * rs2 + rs3 337def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), 338 (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 339 340// fnmadd: -rs1 * rs2 - rs3 341def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), 342 (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 343 344// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the 345// canonical NaN when given a signaling NaN. This doesn't match the LLVM 346// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the 347// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that 348// matches LLVM's fminnum and fmaxnum 349// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 350def : PatFpr32Fpr32<fminnum, FMIN_S>; 351def : PatFpr32Fpr32<fmaxnum, FMAX_S>; 352 353/// Setcc 354 355def : PatFpr32Fpr32<seteq, FEQ_S>; 356def : PatFpr32Fpr32<setoeq, FEQ_S>; 357def : PatFpr32Fpr32<setlt, FLT_S>; 358def : PatFpr32Fpr32<setolt, FLT_S>; 359def : PatFpr32Fpr32<setle, FLE_S>; 360def : PatFpr32Fpr32<setole, FLE_S>; 361 362// Define pattern expansions for setcc operations which aren't directly 363// handled by a RISC-V instruction and aren't expanded in the SelectionDAG 364// Legalizer. 365 366def : Pat<(seto FPR32:$rs1, FPR32:$rs2), 367 (AND (FEQ_S FPR32:$rs1, FPR32:$rs1), 368 (FEQ_S FPR32:$rs2, FPR32:$rs2))>; 369def : Pat<(seto FPR32:$rs1, FPR32:$rs1), 370 (FEQ_S $rs1, $rs1)>; 371 372def : Pat<(setuo FPR32:$rs1, FPR32:$rs2), 373 (SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1), 374 (FEQ_S FPR32:$rs2, FPR32:$rs2)), 375 1)>; 376def : Pat<(setuo FPR32:$rs1, FPR32:$rs1), 377 (SLTIU (FEQ_S $rs1, $rs1), 1)>; 378 379def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>; 380 381/// Loads 382 383defm : LdPat<load, FLW>; 384 385/// Stores 386 387defm : StPat<store, FSW, FPR32>; 388 389} // Predicates = [HasStdExtF] 390 391let Predicates = [HasStdExtF, IsRV32] in { 392// float->[u]int. Round-to-zero must be used. 393def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 394def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 395 396// [u]int->float. Match GCC and default to using dynamic rounding mode. 397def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>; 398def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>; 399} // Predicates = [HasStdExtF, IsRV32] 400 401let Predicates = [HasStdExtF, IsRV64] in { 402def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; 403def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; 404def : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)), 405 (FMV_X_W FPR32:$src)>; 406 407// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe 408// because fpto[u|s]i produces poison if the value can't fit into the target. 409// We match the single case below because fcvt.wu.s sign-extends its result so 410// is cheaper than fcvt.lu.s+sext.w. 411def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32), 412 (FCVT_WU_S $rs1, 0b001)>; 413 414// FP->[u]int64 415def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>; 416def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>; 417 418// [u]int->fp. Match GCC and default to using dynamic rounding mode. 419def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_S_W $rs1, 0b111)>; 420def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; 421def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>; 422def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>; 423} // Predicates = [HasStdExtF, IsRV64] 424