1//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'F', 10// Single-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVFMV_W_X_RV64 19 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>; 20def SDT_RISCVFMV_X_ANYEXTW_RV64 21 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>; 22def SDT_RISCVFCVT_W_RV64 23 : SDTypeProfile<1, 2, [SDTCisVT<0, i64>, SDTCisFP<1>, 24 SDTCisVT<2, i64>]>; 25def SDT_RISCVFCVT_X 26 : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisFP<1>, 27 SDTCisVT<2, XLenVT>]>; 28 29def SDT_RISCVFROUND 30 : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, XLenVT>]>; 32 33def riscv_fround 34 : SDNode<"RISCVISD::FROUND", SDT_RISCVFROUND>; 35 36def riscv_fmv_w_x_rv64 37 : SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>; 38def riscv_fmv_x_anyextw_rv64 39 : SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>; 40def riscv_fcvt_w_rv64 41 : SDNode<"RISCVISD::FCVT_W_RV64", SDT_RISCVFCVT_W_RV64>; 42def riscv_fcvt_wu_rv64 43 : SDNode<"RISCVISD::FCVT_WU_RV64", SDT_RISCVFCVT_W_RV64>; 44def riscv_fcvt_x 45 : SDNode<"RISCVISD::FCVT_X", SDT_RISCVFCVT_X>; 46def riscv_fcvt_xu 47 : SDNode<"RISCVISD::FCVT_XU", SDT_RISCVFCVT_X>; 48 49def riscv_strict_fcvt_w_rv64 50 : SDNode<"RISCVISD::STRICT_FCVT_W_RV64", SDT_RISCVFCVT_W_RV64, 51 [SDNPHasChain]>; 52def riscv_strict_fcvt_wu_rv64 53 : SDNode<"RISCVISD::STRICT_FCVT_WU_RV64", SDT_RISCVFCVT_W_RV64, 54 [SDNPHasChain]>; 55 56def riscv_any_fcvt_w_rv64 : PatFrags<(ops node:$src, node:$frm), 57 [(riscv_strict_fcvt_w_rv64 node:$src, node:$frm), 58 (riscv_fcvt_w_rv64 node:$src, node:$frm)]>; 59def riscv_any_fcvt_wu_rv64 : PatFrags<(ops node:$src, node:$frm), 60 [(riscv_strict_fcvt_wu_rv64 node:$src, node:$frm), 61 (riscv_fcvt_wu_rv64 node:$src, node:$frm)]>; 62 63def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3), 64 (any_fma node:$rs1, node:$rs2, node:$rs3), [{ 65 return N->getFlags().hasNoSignedZeros(); 66}]>; 67//===----------------------------------------------------------------------===// 68// Operand and SDNode transformation definitions. 69//===----------------------------------------------------------------------===// 70 71// Zfinx 72 73def GPRAsFPR : AsmOperandClass { 74 let Name = "GPRAsFPR"; 75 let ParserMethod = "parseGPRAsFPR"; 76 let RenderMethod = "addRegOperands"; 77} 78 79def FPR32INX : RegisterOperand<GPRF32> { 80 let ParserMatchClass = GPRAsFPR; 81 let DecoderMethod = "DecodeGPRRegisterClass"; 82} 83 84// inx = 0 : f, d, zfh, zfhmin 85// = 1 : zfinx, zdinx, zhinx, zhinxmin 86// = 2 : zdinx_rv32 87class ExtInfo<bits<2> inx, list<Predicate> pres> { 88 string Suffix = !cond(!eq(inx, 0): "", 89 !eq(inx, 1): "_INX", 90 !eq(inx, 2): "_IN32X"); 91 list<Predicate> Predicates = pres; 92 string Space = !cond(!eq(inx, 0): "", 93 !eq(inx, 1): "RVZfinx", 94 !eq(inx, 2): "RV32Zdinx"); 95} 96 97class ExtInfo_r<ExtInfo ext, DAGOperand reg> { 98 string Suffix = ext.Suffix; 99 list<Predicate> Predicates = ext.Predicates; 100 string Space = ext.Space; 101 DAGOperand Reg = reg; 102} 103 104class ExtInfo_rr<ExtInfo ext, DAGOperand rdty, DAGOperand rs1ty> { 105 string Suffix = ext.Suffix; 106 list<Predicate> Predicates = ext.Predicates; 107 string Space = ext.Space; 108 DAGOperand RdTy = rdty; 109 DAGOperand Rs1Ty = rs1ty; 110} 111 112def FExt : ExtInfo<0, [HasStdExtF]>; 113def F64Ext : ExtInfo<0, [HasStdExtF, IsRV64]>; 114def ZfinxExt : ExtInfo<1, [HasStdExtZfinx]>; 115def Zfinx64Ext : ExtInfo<1, [HasStdExtZfinx, IsRV64]>; 116 117def F : ExtInfo_r<FExt, FPR32>; 118def F_INX : ExtInfo_r<ZfinxExt, FPR32INX>; 119 120def FF : ExtInfo_rr<FExt, FPR32, FPR32>; 121def FF_INX : ExtInfo_rr<ZfinxExt, FPR32INX, FPR32INX>; 122def FX : ExtInfo_rr<FExt, FPR32, GPR>; 123def FX_INX : ExtInfo_rr<ZfinxExt, FPR32INX, GPR>; 124def FX_64 : ExtInfo_rr<F64Ext, FPR32, GPR>; 125def FX_INX_64 : ExtInfo_rr<Zfinx64Ext, FPR32INX, GPR>; 126def XF : ExtInfo_rr<FExt, GPR, FPR32>; 127def XF_64 : ExtInfo_rr<F64Ext, GPR, FPR32>; 128def XF_INX : ExtInfo_rr<ZfinxExt, GPR, FPR32INX>; 129def XF_INX_64 : ExtInfo_rr<Zfinx64Ext, GPR, FPR32INX>; 130 131defvar FINX = [F, F_INX]; 132defvar FFINX = [FF, FF_INX]; 133defvar FXINX = [FX, FX_INX]; 134defvar XFINX = [XF, XF_INX]; 135defvar XFIN64X = [XF_64, XF_INX_64]; 136defvar FXIN64X = [FX_64, FX_INX_64]; 137 138// Floating-point rounding mode 139 140def FRMArg : AsmOperandClass { 141 let Name = "FRMArg"; 142 let RenderMethod = "addFRMArgOperands"; 143 let DiagnosticType = "InvalidFRMArg"; 144} 145 146def frmarg : Operand<XLenVT> { 147 let ParserMatchClass = FRMArg; 148 let PrintMethod = "printFRMArg"; 149 let DecoderMethod = "decodeFRMArg"; 150} 151 152//===----------------------------------------------------------------------===// 153// Instruction class templates 154//===----------------------------------------------------------------------===// 155 156let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 157class FPLoad_r<bits<3> funct3, string opcodestr, RegisterClass rty, 158 SchedWrite sw> 159 : RVInstI<funct3, OPC_LOAD_FP, (outs rty:$rd), 160 (ins GPRMem:$rs1, simm12:$imm12), 161 opcodestr, "$rd, ${imm12}(${rs1})">, 162 Sched<[sw, ReadFMemBase]>; 163 164let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 165class FPStore_r<bits<3> funct3, string opcodestr, RegisterClass rty, 166 SchedWrite sw> 167 : RVInstS<funct3, OPC_STORE_FP, (outs), 168 (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12), 169 opcodestr, "$rs2, ${imm12}(${rs1})">, 170 Sched<[sw, ReadFStoreData, ReadFMemBase]>; 171 172let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, 173 UseNamedOperandTable = 1, hasPostISelHook = 1, isCommutable = 1 in 174class FPFMA_rrr_frm<RISCVOpcode opcode, bits<2> funct2, string opcodestr, 175 DAGOperand rty> 176 : RVInstR4Frm<funct2, opcode, (outs rty:$rd), 177 (ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm), 178 opcodestr, "$rd, $rs1, $rs2, $rs3, $frm">; 179 180multiclass FPFMA_rrr_frm_m<RISCVOpcode opcode, bits<2> funct2, 181 string opcodestr, list<ExtInfo_r> Exts> { 182 foreach Ext = Exts in 183 let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in 184 def Ext.Suffix : FPFMA_rrr_frm<opcode, funct2, opcodestr, Ext.Reg>; 185} 186 187class FPFMADynFrmAlias<FPFMA_rrr_frm Inst, string OpcodeStr, 188 DAGOperand rty> 189 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 190 (Inst rty:$rd, rty:$rs1, rty:$rs2, rty:$rs3, 0b111)>; 191multiclass FPFMADynFrmAlias_m<FPFMA_rrr_frm Inst, string OpcodeStr, 192 list<ExtInfo_r> Exts> { 193 foreach Ext = Exts in 194 let Predicates = Ext.Predicates in 195 def : FPFMADynFrmAlias<!cast<FPFMA_rrr_frm>(Inst#Ext.Suffix), OpcodeStr, 196 Ext.Reg>; 197} 198 199let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in 200class FPALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr, 201 DAGOperand rty, bit Commutable> 202 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rty:$rd), 203 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> { 204 let isCommutable = Commutable; 205} 206multiclass FPALU_rr_m<bits<7> funct7, bits<3> funct3, string opcodestr, 207 list<ExtInfo_r> Exts, bit Commutable = 0> { 208 foreach Ext = Exts in 209 let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in 210 def Ext.Suffix : FPALU_rr<funct7, funct3, opcodestr, Ext.Reg, Commutable>; 211} 212 213let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, 214 UseNamedOperandTable = 1, hasPostISelHook = 1 in 215class FPALU_rr_frm<bits<7> funct7, string opcodestr, DAGOperand rty, 216 bit Commutable> 217 : RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd), 218 (ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr, 219 "$rd, $rs1, $rs2, $frm"> { 220 let isCommutable = Commutable; 221} 222multiclass FPALU_rr_frm_m<bits<7> funct7, string opcodestr, 223 list<ExtInfo_r> Exts, bit Commutable = 0> { 224 foreach Ext = Exts in 225 let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in 226 def Ext.Suffix : FPALU_rr_frm<funct7, opcodestr, Ext.Reg, Commutable>; 227} 228 229class FPALUDynFrmAlias<FPALU_rr_frm Inst, string OpcodeStr, 230 DAGOperand rty> 231 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 232 (Inst rty:$rd, rty:$rs1, rty:$rs2, 0b111)>; 233multiclass FPALUDynFrmAlias_m<FPALU_rr_frm Inst, string OpcodeStr, 234 list<ExtInfo_r> Exts> { 235 foreach Ext = Exts in 236 let Predicates = Ext.Predicates in 237 def : FPALUDynFrmAlias<!cast<FPALU_rr_frm>(Inst#Ext.Suffix), OpcodeStr, 238 Ext.Reg>; 239} 240 241let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in 242class FPUnaryOp_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3, 243 DAGOperand rdty, DAGOperand rs1ty, string opcodestr> 244 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1), 245 opcodestr, "$rd, $rs1"> { 246 let rs2 = rs2val; 247} 248multiclass FPUnaryOp_r_m<bits<7> funct7, bits<5> rs2val, bits<3> funct3, 249 list<ExtInfo_rr> Exts, string opcodestr> { 250 foreach Ext = Exts in 251 let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in 252 def Ext.Suffix : FPUnaryOp_r<funct7, rs2val, funct3, Ext.RdTy, Ext.Rs1Ty, 253 opcodestr>; 254} 255 256let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, 257 UseNamedOperandTable = 1, hasPostISelHook = 1 in 258class FPUnaryOp_r_frm<bits<7> funct7, bits<5> rs2val, DAGOperand rdty, 259 DAGOperand rs1ty, string opcodestr> 260 : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd), 261 (ins rs1ty:$rs1, frmarg:$frm), opcodestr, 262 "$rd, $rs1, $frm"> { 263 let rs2 = rs2val; 264} 265multiclass FPUnaryOp_r_frm_m<bits<7> funct7, bits<5> rs2val, 266 list<ExtInfo_rr> Exts, string opcodestr> { 267 foreach Ext = Exts in 268 let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in 269 def Ext.Suffix : FPUnaryOp_r_frm<funct7, rs2val, Ext.RdTy, Ext.Rs1Ty, 270 opcodestr>; 271} 272 273class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr, 274 DAGOperand rdty, DAGOperand rs1ty> 275 : InstAlias<OpcodeStr#" $rd, $rs1", 276 (Inst rdty:$rd, rs1ty:$rs1, 0b111)>; 277multiclass FPUnaryOpDynFrmAlias_m<FPUnaryOp_r_frm Inst, string OpcodeStr, 278 list<ExtInfo_rr> Exts> { 279 foreach Ext = Exts in 280 let Predicates = Ext.Predicates in 281 def : FPUnaryOpDynFrmAlias<!cast<FPUnaryOp_r_frm>(Inst#Ext.Suffix), 282 OpcodeStr, Ext.RdTy, Ext.Rs1Ty>; 283} 284 285let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, 286 IsSignExtendingOpW = 1 in 287class FPCmp_rr<bits<7> funct7, bits<3> funct3, string opcodestr, 288 DAGOperand rty, bit Commutable> 289 : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd), 290 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> { 291 let isCommutable = Commutable; 292} 293multiclass FPCmp_rr_m<bits<7> funct7, bits<3> funct3, string opcodestr, 294 list<ExtInfo_r> Exts, bit Commutable = 0> { 295 foreach Ext = Exts in 296 let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in 297 def Ext.Suffix : FPCmp_rr<funct7, funct3, opcodestr, Ext.Reg, Commutable>; 298} 299 300class PseudoFROUND<RegisterClass Ty> 301 : Pseudo<(outs Ty:$rd), (ins Ty:$rs1, Ty:$rs2, ixlenimm:$rm), 302 [(set Ty:$rd, (riscv_fround Ty:$rs1, Ty:$rs2, timm:$rm))]> { 303 let hasSideEffects = 0; 304 let mayLoad = 0; 305 let mayStore = 0; 306 let usesCustomInserter = 1; 307 let mayRaiseFPException = 1; 308} 309 310//===----------------------------------------------------------------------===// 311// Instructions 312//===----------------------------------------------------------------------===// 313 314let Predicates = [HasStdExtF] in { 315def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>; 316 317// Operands for stores are in the order srcreg, base, offset rather than 318// reflecting the order these fields are specified in the instruction 319// encoding. 320def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>; 321} // Predicates = [HasStdExtF] 322 323let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in { 324defm FMADD_S : FPFMA_rrr_frm_m<OPC_MADD, 0b00, "fmadd.s", FINX>; 325defm FMSUB_S : FPFMA_rrr_frm_m<OPC_MSUB, 0b00, "fmsub.s", FINX>; 326defm FNMSUB_S : FPFMA_rrr_frm_m<OPC_NMSUB, 0b00, "fnmsub.s", FINX>; 327defm FNMADD_S : FPFMA_rrr_frm_m<OPC_NMADD, 0b00, "fnmadd.s", FINX>; 328} 329 330defm : FPFMADynFrmAlias_m<FMADD_S, "fmadd.s", FINX>; 331defm : FPFMADynFrmAlias_m<FMSUB_S, "fmsub.s", FINX>; 332defm : FPFMADynFrmAlias_m<FNMSUB_S, "fnmsub.s", FINX>; 333defm : FPFMADynFrmAlias_m<FNMADD_S, "fnmadd.s", FINX>; 334 335let SchedRW = [WriteFAdd32, ReadFAdd32, ReadFAdd32] in { 336defm FADD_S : FPALU_rr_frm_m<0b0000000, "fadd.s", FINX, /*Commutable*/1>; 337defm FSUB_S : FPALU_rr_frm_m<0b0000100, "fsub.s", FINX>; 338} 339let SchedRW = [WriteFMul32, ReadFMul32, ReadFMul32] in 340defm FMUL_S : FPALU_rr_frm_m<0b0001000, "fmul.s", FINX, /*Commutable*/1>; 341 342let SchedRW = [WriteFDiv32, ReadFDiv32, ReadFDiv32] in 343defm FDIV_S : FPALU_rr_frm_m<0b0001100, "fdiv.s", FINX>; 344 345defm : FPALUDynFrmAlias_m<FADD_S, "fadd.s", FINX>; 346defm : FPALUDynFrmAlias_m<FSUB_S, "fsub.s", FINX>; 347defm : FPALUDynFrmAlias_m<FMUL_S, "fmul.s", FINX>; 348defm : FPALUDynFrmAlias_m<FDIV_S, "fdiv.s", FINX>; 349 350defm FSQRT_S : FPUnaryOp_r_frm_m<0b0101100, 0b00000, FFINX, "fsqrt.s">, 351 Sched<[WriteFSqrt32, ReadFSqrt32]>; 352defm : FPUnaryOpDynFrmAlias_m<FSQRT_S, "fsqrt.s", FFINX>; 353 354let SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32], 355 mayRaiseFPException = 0 in { 356defm FSGNJ_S : FPALU_rr_m<0b0010000, 0b000, "fsgnj.s", FINX>; 357defm FSGNJN_S : FPALU_rr_m<0b0010000, 0b001, "fsgnjn.s", FINX>; 358defm FSGNJX_S : FPALU_rr_m<0b0010000, 0b010, "fsgnjx.s", FINX>; 359} 360 361let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in { 362defm FMIN_S : FPALU_rr_m<0b0010100, 0b000, "fmin.s", FINX, /*Commutable*/1>; 363defm FMAX_S : FPALU_rr_m<0b0010100, 0b001, "fmax.s", FINX, /*Commutable*/1>; 364} 365 366let IsSignExtendingOpW = 1 in 367defm FCVT_W_S : FPUnaryOp_r_frm_m<0b1100000, 0b00000, XFINX, "fcvt.w.s">, 368 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>; 369defm : FPUnaryOpDynFrmAlias_m<FCVT_W_S, "fcvt.w.s", XFINX>; 370 371let IsSignExtendingOpW = 1 in 372defm FCVT_WU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00001, XFINX, "fcvt.wu.s">, 373 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>; 374defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_S, "fcvt.wu.s", XFINX>; 375 376let Predicates = [HasStdExtF], mayRaiseFPException = 0, 377 IsSignExtendingOpW = 1 in 378def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">, 379 Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>; 380 381let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in { 382defm FEQ_S : FPCmp_rr_m<0b1010000, 0b010, "feq.s", FINX, /*Commutable*/1>; 383defm FLT_S : FPCmp_rr_m<0b1010000, 0b001, "flt.s", FINX>; 384defm FLE_S : FPCmp_rr_m<0b1010000, 0b000, "fle.s", FINX>; 385} 386 387let mayRaiseFPException = 0 in 388defm FCLASS_S : FPUnaryOp_r_m<0b1110000, 0b00000, 0b001, XFINX, "fclass.s">, 389 Sched<[WriteFClass32, ReadFClass32]>; 390 391defm FCVT_S_W : FPUnaryOp_r_frm_m<0b1101000, 0b00000, FXINX, "fcvt.s.w">, 392 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>; 393defm : FPUnaryOpDynFrmAlias_m<FCVT_S_W, "fcvt.s.w", FXINX>; 394 395defm FCVT_S_WU : FPUnaryOp_r_frm_m<0b1101000, 0b00001, FXINX, "fcvt.s.wu">, 396 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>; 397defm : FPUnaryOpDynFrmAlias_m<FCVT_S_WU, "fcvt.s.wu", FXINX>; 398 399let Predicates = [HasStdExtF], mayRaiseFPException = 0 in 400def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">, 401 Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>; 402 403defm FCVT_L_S : FPUnaryOp_r_frm_m<0b1100000, 0b00010, XFIN64X, "fcvt.l.s">, 404 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>; 405defm : FPUnaryOpDynFrmAlias_m<FCVT_L_S, "fcvt.l.s", XFIN64X>; 406 407defm FCVT_LU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00011, XFIN64X, "fcvt.lu.s">, 408 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>; 409defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_S, "fcvt.lu.s", XFIN64X>; 410 411defm FCVT_S_L : FPUnaryOp_r_frm_m<0b1101000, 0b00010, FXIN64X, "fcvt.s.l">, 412 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>; 413defm : FPUnaryOpDynFrmAlias_m<FCVT_S_L, "fcvt.s.l", FXIN64X>; 414 415defm FCVT_S_LU : FPUnaryOp_r_frm_m<0b1101000, 0b00011, FXIN64X, "fcvt.s.lu">, 416 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>; 417defm : FPUnaryOpDynFrmAlias_m<FCVT_S_LU, "fcvt.s.lu", FXIN64X>; 418 419//===----------------------------------------------------------------------===// 420// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 421//===----------------------------------------------------------------------===// 422 423let Predicates = [HasStdExtF] in { 424def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>; 425def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>; 426 427def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 428def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 429def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 430 431// fgt.s/fge.s are recognised by the GNU assembler but the canonical 432// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. 433def : InstAlias<"fgt.s $rd, $rs, $rt", 434 (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 435def : InstAlias<"fge.s $rd, $rs, $rt", 436 (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 437 438// The following csr instructions actually alias instructions from the base ISA. 439// However, it only makes sense to support them when the F extension is enabled. 440// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr". 441def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>; 442def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>; 443def : InstAlias<"fscsr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 2>; 444 445// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them 446// zero weight. 447def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>; 448def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>; 449def : InstAlias<"fssr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 0>; 450 451def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, SysRegFRM.Encoding, X0), 2>; 452def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>; 453def : InstAlias<"fsrm $rs", (CSRRW X0, SysRegFRM.Encoding, GPR:$rs), 2>; 454def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>; 455def : InstAlias<"fsrmi $imm", (CSRRWI X0, SysRegFRM.Encoding, uimm5:$imm), 2>; 456 457def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, SysRegFFLAGS.Encoding, X0), 2>; 458def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>; 459def : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>; 460def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>; 461def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>; 462 463// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both 464// spellings should be supported by standard tools. 465def : MnemonicAlias<"fmv.s.x", "fmv.w.x">; 466def : MnemonicAlias<"fmv.x.s", "fmv.x.w">; 467 468def PseudoFLW : PseudoFloatLoad<"flw", FPR32>; 469def PseudoFSW : PseudoStore<"fsw", FPR32>; 470let usesCustomInserter = 1 in { 471def PseudoQuietFLE_S : PseudoQuietFCMP<FPR32>; 472def PseudoQuietFLT_S : PseudoQuietFCMP<FPR32>; 473} 474} // Predicates = [HasStdExtF] 475 476let Predicates = [HasStdExtZfinx] in { 477def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>; 478def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>; 479 480def : InstAlias<"fgt.s $rd, $rs, $rt", 481 (FLT_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>; 482def : InstAlias<"fge.s $rd, $rs, $rt", 483 (FLE_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>; 484} // Predicates = [HasStdExtZfinx] 485 486//===----------------------------------------------------------------------===// 487// Pseudo-instructions and codegen patterns 488//===----------------------------------------------------------------------===// 489 490/// Floating point constants 491def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 492def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; 493 494/// Generic pattern classes 495class PatSetCC<RegisterClass Ty, SDPatternOperator OpNode, CondCode Cond, RVInst Inst> 496 : Pat<(OpNode Ty:$rs1, Ty:$rs2, Cond), (Inst $rs1, $rs2)>; 497 498class PatFprFpr<SDPatternOperator OpNode, RVInstR Inst, 499 RegisterClass RegTy> 500 : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>; 501 502class PatFprFprDynFrm<SDPatternOperator OpNode, RVInstRFrm Inst, 503 RegisterClass RegTy> 504 : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2, 0b111)>; 505 506let Predicates = [HasStdExtF] in { 507 508/// Float constants 509def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>; 510def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0))>; 511 512/// Float conversion operations 513 514// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 515// are defined later. 516 517/// Float arithmetic operations 518 519def : PatFprFprDynFrm<any_fadd, FADD_S, FPR32>; 520def : PatFprFprDynFrm<any_fsub, FSUB_S, FPR32>; 521def : PatFprFprDynFrm<any_fmul, FMUL_S, FPR32>; 522def : PatFprFprDynFrm<any_fdiv, FDIV_S, FPR32>; 523 524def : Pat<(any_fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; 525 526def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; 527def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; 528 529def : PatFprFpr<fcopysign, FSGNJ_S, FPR32>; 530def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; 531 532// fmadd: rs1 * rs2 + rs3 533def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3), 534 (FMADD_S $rs1, $rs2, $rs3, 0b111)>; 535 536// fmsub: rs1 * rs2 - rs3 537def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), 538 (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 539 540// fnmsub: -rs1 * rs2 + rs3 541def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), 542 (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 543 544// fnmadd: -rs1 * rs2 - rs3 545def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), 546 (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 547 548// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 549def : Pat<(fneg (any_fma_nsz FPR32:$rs1, FPR32:$rs2, FPR32:$rs3)), 550 (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 551 552// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 553// LLVM's fminnum and fmaxnum 554// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 555def : PatFprFpr<fminnum, FMIN_S, FPR32>; 556def : PatFprFpr<fmaxnum, FMAX_S, FPR32>; 557 558/// Setcc 559// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for 560// strict versions of those. 561 562// Match non-signaling FEQ_S 563def : PatSetCC<FPR32, any_fsetcc, SETEQ, FEQ_S>; 564def : PatSetCC<FPR32, any_fsetcc, SETOEQ, FEQ_S>; 565def : PatSetCC<FPR32, strict_fsetcc, SETLT, PseudoQuietFLT_S>; 566def : PatSetCC<FPR32, strict_fsetcc, SETOLT, PseudoQuietFLT_S>; 567def : PatSetCC<FPR32, strict_fsetcc, SETLE, PseudoQuietFLE_S>; 568def : PatSetCC<FPR32, strict_fsetcc, SETOLE, PseudoQuietFLE_S>; 569 570// Match signaling FEQ_S 571def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ), 572 (AND (FLE_S $rs1, $rs2), 573 (FLE_S $rs2, $rs1))>; 574def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ), 575 (AND (FLE_S $rs1, $rs2), 576 (FLE_S $rs2, $rs1))>; 577// If both operands are the same, use a single FLE. 578def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ), 579 (FLE_S $rs1, $rs1)>; 580def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ), 581 (FLE_S $rs1, $rs1)>; 582 583def : PatSetCC<FPR32, any_fsetccs, SETLT, FLT_S>; 584def : PatSetCC<FPR32, any_fsetccs, SETOLT, FLT_S>; 585def : PatSetCC<FPR32, any_fsetccs, SETLE, FLE_S>; 586def : PatSetCC<FPR32, any_fsetccs, SETOLE, FLE_S>; 587 588defm Select_FPR32 : SelectCC_GPR_rrirr<FPR32>; 589 590def PseudoFROUND_S : PseudoFROUND<FPR32>; 591 592/// Loads 593 594defm : LdPat<load, FLW, f32>; 595 596/// Stores 597 598defm : StPat<store, FSW, FPR32, f32>; 599 600} // Predicates = [HasStdExtF] 601 602let Predicates = [HasStdExtF, IsRV32] in { 603// Moves (no conversion) 604def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>; 605def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>; 606 607// float->[u]int. Round-to-zero must be used. 608def : Pat<(i32 (any_fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>; 609def : Pat<(i32 (any_fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>; 610 611// Saturating float->[u]int32. 612def : Pat<(i32 (riscv_fcvt_x FPR32:$rs1, timm:$frm)), (FCVT_W_S $rs1, timm:$frm)>; 613def : Pat<(i32 (riscv_fcvt_xu FPR32:$rs1, timm:$frm)), (FCVT_WU_S $rs1, timm:$frm)>; 614 615// float->int32 with current rounding mode. 616def : Pat<(i32 (any_lrint FPR32:$rs1)), (FCVT_W_S $rs1, 0b111)>; 617 618// float->int32 rounded to nearest with ties rounded away from zero. 619def : Pat<(i32 (any_lround FPR32:$rs1)), (FCVT_W_S $rs1, 0b100)>; 620 621// [u]int->float. Match GCC and default to using dynamic rounding mode. 622def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>; 623def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; 624} // Predicates = [HasStdExtF, IsRV32] 625 626let Predicates = [HasStdExtF, IsRV64] in { 627// Moves (no conversion) 628def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; 629def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; 630def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32), 631 (FMV_X_W FPR32:$src)>; 632 633// Use target specific isd nodes to help us remember the result is sign 634// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 635// duplicated if it has another user that didn't need the sign_extend. 636def : Pat<(riscv_any_fcvt_w_rv64 FPR32:$rs1, timm:$frm), (FCVT_W_S $rs1, timm:$frm)>; 637def : Pat<(riscv_any_fcvt_wu_rv64 FPR32:$rs1, timm:$frm), (FCVT_WU_S $rs1, timm:$frm)>; 638 639// float->[u]int64. Round-to-zero must be used. 640def : Pat<(i64 (any_fp_to_sint FPR32:$rs1)), (FCVT_L_S $rs1, 0b001)>; 641def : Pat<(i64 (any_fp_to_uint FPR32:$rs1)), (FCVT_LU_S $rs1, 0b001)>; 642 643// Saturating float->[u]int64. 644def : Pat<(i64 (riscv_fcvt_x FPR32:$rs1, timm:$frm)), (FCVT_L_S $rs1, timm:$frm)>; 645def : Pat<(i64 (riscv_fcvt_xu FPR32:$rs1, timm:$frm)), (FCVT_LU_S $rs1, timm:$frm)>; 646 647// float->int64 with current rounding mode. 648def : Pat<(i64 (any_lrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>; 649def : Pat<(i64 (any_llrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>; 650 651// float->int64 rounded to neartest with ties rounded away from zero. 652def : Pat<(i64 (any_lround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>; 653def : Pat<(i64 (any_llround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>; 654 655// [u]int->fp. Match GCC and default to using dynamic rounding mode. 656def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W $rs1, 0b111)>; 657def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>; 658def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>; 659def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>; 660} // Predicates = [HasStdExtF, IsRV64] 661