1//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'F', 10// Single-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVFMV_W_X_RV64 19 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>; 20def SDT_RISCVFMV_X_ANYEXTW_RV64 21 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>; 22 23def riscv_fmv_w_x_rv64 24 : SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>; 25def riscv_fmv_x_anyextw_rv64 26 : SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>; 27 28//===----------------------------------------------------------------------===// 29// Operand and SDNode transformation definitions. 30//===----------------------------------------------------------------------===// 31 32// Floating-point rounding mode 33 34def FRMArg : AsmOperandClass { 35 let Name = "FRMArg"; 36 let RenderMethod = "addFRMArgOperands"; 37 let DiagnosticType = "InvalidFRMArg"; 38} 39 40def frmarg : Operand<XLenVT> { 41 let ParserMatchClass = FRMArg; 42 let PrintMethod = "printFRMArg"; 43 let DecoderMethod = "decodeFRMArg"; 44} 45 46//===----------------------------------------------------------------------===// 47// Instruction class templates 48//===----------------------------------------------------------------------===// 49 50let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 51class FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr> 52 : RVInstR4<0b00, opcode, (outs FPR32:$rd), 53 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3), 54 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 55 56class FPFMASDynFrmAlias<FPFMAS_rrr_frm Inst, string OpcodeStr> 57 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 58 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 59 60let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 61class FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 62 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd), 63 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">; 64 65let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 66class FPALUS_rr_frm<bits<7> funct7, string opcodestr> 67 : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd), 68 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr, 69 "$rd, $rs1, $rs2, $funct3">; 70 71class FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr> 72 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 73 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>; 74 75let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 76class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty, 77 RegisterClass rs1ty, string opcodestr> 78 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1), 79 opcodestr, "$rd, $rs1">; 80 81let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 82class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty, 83 string opcodestr> 84 : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd), 85 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr, 86 "$rd, $rs1, $funct3">; 87 88class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr, 89 RegisterClass rdty, RegisterClass rs1ty> 90 : InstAlias<OpcodeStr#" $rd, $rs1", 91 (Inst rdty:$rd, rs1ty:$rs1, 0b111)>; 92 93let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 94class FPCmpS_rr<bits<3> funct3, string opcodestr> 95 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd), 96 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">; 97 98//===----------------------------------------------------------------------===// 99// Instructions 100//===----------------------------------------------------------------------===// 101 102let Predicates = [HasStdExtF] in { 103let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 104def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd), 105 (ins GPR:$rs1, simm12:$imm12), 106 "flw", "$rd, ${imm12}(${rs1})">; 107 108// Operands for stores are in the order srcreg, base, offset rather than 109// reflecting the order these fields are specified in the instruction 110// encoding. 111let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 112def FSW : RVInstS<0b010, OPC_STORE_FP, (outs), 113 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12), 114 "fsw", "$rs2, ${imm12}(${rs1})">; 115 116def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">; 117def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">; 118def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">; 119def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">; 120def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">; 121def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">; 122def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">; 123def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">; 124 125def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">; 126def : FPALUSDynFrmAlias<FADD_S, "fadd.s">; 127def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">; 128def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">; 129def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">; 130def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">; 131def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">; 132def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">; 133 134def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s"> { 135 let rs2 = 0b00000; 136} 137def : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>; 138 139def FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">; 140def FSGNJN_S : FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">; 141def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">; 142def FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">; 143def FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">; 144 145def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s"> { 146 let rs2 = 0b00000; 147} 148def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>; 149 150def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s"> { 151 let rs2 = 0b00001; 152} 153def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>; 154 155def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w"> { 156 let rs2 = 0b00000; 157} 158 159def FEQ_S : FPCmpS_rr<0b010, "feq.s">; 160def FLT_S : FPCmpS_rr<0b001, "flt.s">; 161def FLE_S : FPCmpS_rr<0b000, "fle.s">; 162 163def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s"> { 164 let rs2 = 0b00000; 165} 166 167def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w"> { 168 let rs2 = 0b00000; 169} 170def : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>; 171 172def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu"> { 173 let rs2 = 0b00001; 174} 175def : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>; 176 177def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x"> { 178 let rs2 = 0b00000; 179} 180} // Predicates = [HasStdExtF] 181 182let Predicates = [HasStdExtF, IsRV64] in { 183def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s"> { 184 let rs2 = 0b00010; 185} 186def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>; 187 188def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s"> { 189 let rs2 = 0b00011; 190} 191def : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>; 192 193def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l"> { 194 let rs2 = 0b00010; 195} 196def : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>; 197 198def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu"> { 199 let rs2 = 0b00011; 200} 201def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>; 202} // Predicates = [HasStdExtF, IsRV64] 203 204//===----------------------------------------------------------------------===// 205// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 206//===----------------------------------------------------------------------===// 207 208let Predicates = [HasStdExtF] in { 209def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>; 210def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>; 211 212def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 213def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 214def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 215 216// fgt.s/fge.s are recognised by the GNU assembler but the canonical 217// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. 218def : InstAlias<"fgt.s $rd, $rs, $rt", 219 (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 220def : InstAlias<"fge.s $rd, $rs, $rt", 221 (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 222 223// The following csr instructions actually alias instructions from the base ISA. 224// However, it only makes sense to support them when the F extension is enabled. 225// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr". 226def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 2>; 227def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs)>; 228def : InstAlias<"fscsr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 2>; 229 230// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them 231// zero weight. 232def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, FCSR.Encoding, X0), 0>; 233def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, FCSR.Encoding, GPR:$rs), 0>; 234def : InstAlias<"fssr $rs", (CSRRW X0, FCSR.Encoding, GPR:$rs), 0>; 235 236def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, FRM.Encoding, X0), 2>; 237def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, FRM.Encoding, GPR:$rs)>; 238def : InstAlias<"fsrm $rs", (CSRRW X0, FRM.Encoding, GPR:$rs), 2>; 239def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, FRM.Encoding, uimm5:$imm)>; 240def : InstAlias<"fsrmi $imm", (CSRRWI X0, FRM.Encoding, uimm5:$imm), 2>; 241 242def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, FFLAGS.Encoding, X0), 2>; 243def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, FFLAGS.Encoding, GPR:$rs)>; 244def : InstAlias<"fsflags $rs", (CSRRW X0, FFLAGS.Encoding, GPR:$rs), 2>; 245def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, FFLAGS.Encoding, uimm5:$imm)>; 246def : InstAlias<"fsflagsi $imm", (CSRRWI X0, FFLAGS.Encoding, uimm5:$imm), 2>; 247 248// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both 249// spellings should be supported by standard tools. 250def : MnemonicAlias<"fmv.s.x", "fmv.w.x">; 251def : MnemonicAlias<"fmv.x.s", "fmv.x.w">; 252 253def PseudoFLW : PseudoFloatLoad<"flw", FPR32>; 254def PseudoFSW : PseudoStore<"fsw", FPR32>; 255} // Predicates = [HasStdExtF] 256 257//===----------------------------------------------------------------------===// 258// Pseudo-instructions and codegen patterns 259//===----------------------------------------------------------------------===// 260 261/// Generic pattern classes 262class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst> 263 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>; 264 265class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 266 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>; 267 268let Predicates = [HasStdExtF] in { 269 270/// Float conversion operations 271 272// Moves (no conversion) 273def : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>; 274def : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>; 275 276// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 277// are defined later. 278 279/// Float arithmetic operations 280 281def : PatFpr32Fpr32DynFrm<fadd, FADD_S>; 282def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>; 283def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>; 284def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>; 285 286def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; 287 288def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; 289def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; 290 291def : PatFpr32Fpr32<fcopysign, FSGNJ_S>; 292def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; 293 294// fmadd: rs1 * rs2 + rs3 295def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3), 296 (FMADD_S $rs1, $rs2, $rs3, 0b111)>; 297 298// fmsub: rs1 * rs2 - rs3 299def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), 300 (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 301 302// fnmsub: -rs1 * rs2 + rs3 303def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), 304 (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 305 306// fnmadd: -rs1 * rs2 - rs3 307def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), 308 (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 309 310// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the 311// canonical NaN when given a signaling NaN. This doesn't match the LLVM 312// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the 313// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that 314// matches LLVM's fminnum and fmaxnum 315// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 316def : PatFpr32Fpr32<fminnum, FMIN_S>; 317def : PatFpr32Fpr32<fmaxnum, FMAX_S>; 318 319/// Setcc 320 321def : PatFpr32Fpr32<seteq, FEQ_S>; 322def : PatFpr32Fpr32<setoeq, FEQ_S>; 323def : PatFpr32Fpr32<setlt, FLT_S>; 324def : PatFpr32Fpr32<setolt, FLT_S>; 325def : PatFpr32Fpr32<setle, FLE_S>; 326def : PatFpr32Fpr32<setole, FLE_S>; 327 328// Define pattern expansions for setcc operations which aren't directly 329// handled by a RISC-V instruction and aren't expanded in the SelectionDAG 330// Legalizer. 331 332def : Pat<(seto FPR32:$rs1, FPR32:$rs2), 333 (AND (FEQ_S FPR32:$rs1, FPR32:$rs1), 334 (FEQ_S FPR32:$rs2, FPR32:$rs2))>; 335 336def : Pat<(setuo FPR32:$rs1, FPR32:$rs2), 337 (SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1), 338 (FEQ_S FPR32:$rs2, FPR32:$rs2)), 339 1)>; 340 341def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>; 342 343/// Loads 344 345defm : LdPat<load, FLW>; 346 347/// Stores 348 349defm : StPat<store, FSW, FPR32>; 350 351} // Predicates = [HasStdExtF] 352 353let Predicates = [HasStdExtF, IsRV32] in { 354// float->[u]int. Round-to-zero must be used. 355def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 356def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 357 358// [u]int->float. Match GCC and default to using dynamic rounding mode. 359def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>; 360def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>; 361} // Predicates = [HasStdExtF, IsRV32] 362 363let Predicates = [HasStdExtF, IsRV32] in { 364// FP->[u]int. Round-to-zero must be used 365def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 366def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 367 368// [u]int->fp. Match GCC and default to using dynamic rounding mode. 369def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>; 370def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>; 371} // Predicates = [HasStdExtF, IsRV32] 372 373let Predicates = [HasStdExtF, IsRV64] in { 374def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; 375def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; 376def : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)), 377 (FMV_X_W FPR32:$src)>; 378 379// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe 380// because fpto[u|s]i produces poison if the value can't fit into the target. 381// We match the single case below because fcvt.wu.s sign-extends its result so 382// is cheaper than fcvt.lu.s+sext.w. 383def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32), 384 (FCVT_WU_S $rs1, 0b001)>; 385 386// FP->[u]int64 387def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>; 388def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>; 389 390// [u]int->fp. Match GCC and default to using dynamic rounding mode. 391def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_S_W $rs1, 0b111)>; 392def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; 393def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>; 394def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>; 395} // Predicates = [HasStdExtF, IsRV64] 396