1//===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'D', 10// Double-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 19 SDTCisVT<1, i32>, 20 SDTCisSameAs<1, 2>]>; 21def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, 22 SDTCisVT<1, i32>, 23 SDTCisVT<2, f64>]>; 24 25def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>; 26def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>; 27 28//===----------------------------------------------------------------------===// 29// Operand and SDNode transformation definitions. 30//===----------------------------------------------------------------------===// 31 32// Zdinx 33 34def GPRPF64AsFPR : AsmOperandClass { 35 let Name = "GPRPF64AsFPR"; 36 let ParserMethod = "parseGPRAsFPR"; 37 let RenderMethod = "addRegOperands"; 38} 39 40def GPRF64AsFPR : AsmOperandClass { 41 let Name = "GPRF64AsFPR"; 42 let ParserMethod = "parseGPRAsFPR"; 43 let RenderMethod = "addRegOperands"; 44} 45 46def FPR64INX : RegisterOperand<GPRF64> { 47 let ParserMatchClass = GPRF64AsFPR; 48 let DecoderMethod = "DecodeGPRRegisterClass"; 49} 50 51def FPR64IN32X : RegisterOperand<GPRPF64> { 52 let ParserMatchClass = GPRPF64AsFPR; 53} 54 55def DExt : ExtInfo<0, [HasStdExtD]>; 56def D64Ext : ExtInfo<0, [HasStdExtD, IsRV64]>; 57def ZdinxExt : ExtInfo<1, [HasStdExtZdinx, IsRV64]>; 58def Zdinx32Ext : ExtInfo<2, [HasStdExtZdinx, IsRV32]>; 59 60def D : ExtInfo_r<DExt, FPR64>; 61def D_INX : ExtInfo_r<ZdinxExt, FPR64INX>; 62def D_IN32X : ExtInfo_r<Zdinx32Ext, FPR64IN32X>; 63 64def DD : ExtInfo_rr<DExt, FPR64, FPR64>; 65def DD_INX : ExtInfo_rr<ZdinxExt, FPR64INX, FPR64INX>; 66def DD_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, FPR64IN32X>; 67def DF : ExtInfo_rr<DExt, FPR64, FPR32>; 68def DF_INX : ExtInfo_rr<ZdinxExt, FPR64INX, FPR32INX>; 69def DF_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, FPR32INX>; 70def DX : ExtInfo_rr<DExt, FPR64, GPR>; 71def DX_INX : ExtInfo_rr<ZdinxExt, FPR64INX, GPR>; 72def DX_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, GPR>; 73def DX_64 : ExtInfo_rr<D64Ext, FPR64, GPR>; 74def FD : ExtInfo_rr<DExt, FPR32, FPR64>; 75def FD_INX : ExtInfo_rr<ZdinxExt, FPR32INX, FPR64INX>; 76def FD_IN32X : ExtInfo_rr<Zdinx32Ext, FPR32INX, FPR64IN32X>; 77def XD : ExtInfo_rr<DExt, GPR, FPR64>; 78def XD_INX : ExtInfo_rr<ZdinxExt, GPR, FPR64INX>; 79def XD_IN32X : ExtInfo_rr<Zdinx32Ext, GPR, FPR64IN32X>; 80def XD_64 : ExtInfo_rr<D64Ext, GPR, FPR64>; 81 82defvar DINX = [D, D_INX, D_IN32X]; 83defvar DDINX = [DD, DD_INX, DD_IN32X]; 84defvar DXINX = [DX, DX_INX, DX_IN32X]; 85defvar DFINX = [DF, DF_INX, DF_IN32X]; 86defvar FDINX = [FD, FD_INX, FD_IN32X]; 87defvar XDINX = [XD, XD_INX, XD_IN32X]; 88defvar DXIN64X = [DX_64, DX_INX]; 89defvar XDIN64X = [XD_64, XD_INX]; 90 91//===----------------------------------------------------------------------===// 92// Instructions 93//===----------------------------------------------------------------------===// 94 95let Predicates = [HasStdExtD] in { 96def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>; 97 98// Operands for stores are in the order srcreg, base, offset rather than 99// reflecting the order these fields are specified in the instruction 100// encoding. 101def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>; 102} // Predicates = [HasStdExtD] 103 104let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in { 105defm FMADD_D : FPFMA_rrr_frm_m<OPC_MADD, 0b01, "fmadd.d", DINX>; 106defm FMSUB_D : FPFMA_rrr_frm_m<OPC_MSUB, 0b01, "fmsub.d", DINX>; 107defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", DINX>; 108defm FNMADD_D : FPFMA_rrr_frm_m<OPC_NMADD, 0b01, "fnmadd.d", DINX>; 109} 110 111defm : FPFMADynFrmAlias_m<FMADD_D, "fmadd.d", DINX>; 112defm : FPFMADynFrmAlias_m<FMSUB_D, "fmsub.d", DINX>; 113defm : FPFMADynFrmAlias_m<FNMSUB_D, "fnmsub.d", DINX>; 114defm : FPFMADynFrmAlias_m<FNMADD_D, "fnmadd.d", DINX>; 115 116let SchedRW = [WriteFAdd64, ReadFAdd64, ReadFAdd64] in { 117defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", DINX, /*Commutable*/1>; 118defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", DINX>; 119} 120let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in 121defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", DINX, /*Commutable*/1>; 122 123let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in 124defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", DINX>; 125 126defm : FPALUDynFrmAlias_m<FADD_D, "fadd.d", DINX>; 127defm : FPALUDynFrmAlias_m<FSUB_D, "fsub.d", DINX>; 128defm : FPALUDynFrmAlias_m<FMUL_D, "fmul.d", DINX>; 129defm : FPALUDynFrmAlias_m<FDIV_D, "fdiv.d", DINX>; 130 131defm FSQRT_D : FPUnaryOp_r_frm_m<0b0101101, 0b00000, DDINX, "fsqrt.d">, 132 Sched<[WriteFSqrt64, ReadFSqrt64]>; 133defm : FPUnaryOpDynFrmAlias_m<FSQRT_D, "fsqrt.d", DDINX>; 134 135let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64], 136 mayRaiseFPException = 0 in { 137defm FSGNJ_D : FPALU_rr_m<0b0010001, 0b000, "fsgnj.d", DINX>; 138defm FSGNJN_D : FPALU_rr_m<0b0010001, 0b001, "fsgnjn.d", DINX>; 139defm FSGNJX_D : FPALU_rr_m<0b0010001, 0b010, "fsgnjx.d", DINX>; 140} 141 142let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in { 143defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", DINX, /*Commutable*/1>; 144defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", DINX, /*Commutable*/1>; 145} 146 147defm FCVT_S_D : FPUnaryOp_r_frm_m<0b0100000, 0b00001, FDINX, "fcvt.s.d">, 148 Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>; 149defm : FPUnaryOpDynFrmAlias_m<FCVT_S_D, "fcvt.s.d", FDINX>; 150 151defm FCVT_D_S : FPUnaryOp_r_m<0b0100001, 0b00000, 0b000, DFINX, "fcvt.d.s">, 152 Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>; 153 154let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in { 155defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", DINX, /*Commutable*/1>; 156defm FLT_D : FPCmp_rr_m<0b1010001, 0b001, "flt.d", DINX>; 157defm FLE_D : FPCmp_rr_m<0b1010001, 0b000, "fle.d", DINX>; 158} 159 160defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, XDINX, "fclass.d">, 161 Sched<[WriteFClass64, ReadFClass64]>; 162 163let IsSignExtendingOpW = 1 in 164defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, XDINX, "fcvt.w.d">, 165 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; 166defm : FPUnaryOpDynFrmAlias_m<FCVT_W_D, "fcvt.w.d", XDINX>; 167 168let IsSignExtendingOpW = 1 in 169defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, XDINX, "fcvt.wu.d">, 170 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; 171defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_D, "fcvt.wu.d", XDINX>; 172 173defm FCVT_D_W : FPUnaryOp_r_m<0b1101001, 0b00000, 0b000, DXINX, "fcvt.d.w">, 174 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; 175 176defm FCVT_D_WU : FPUnaryOp_r_m<0b1101001, 0b00001, 0b000, DXINX, "fcvt.d.wu">, 177 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; 178 179defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, XDIN64X, "fcvt.l.d">, 180 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; 181defm : FPUnaryOpDynFrmAlias_m<FCVT_L_D, "fcvt.l.d", XDIN64X>; 182 183defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, XDIN64X, "fcvt.lu.d">, 184 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; 185defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_D, "fcvt.lu.d", XDIN64X>; 186 187let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in 188def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">, 189 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>; 190 191defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, DXIN64X, "fcvt.d.l">, 192 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; 193defm : FPUnaryOpDynFrmAlias_m<FCVT_D_L, "fcvt.d.l", DXIN64X>; 194 195defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, DXIN64X, "fcvt.d.lu">, 196 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; 197defm : FPUnaryOpDynFrmAlias_m<FCVT_D_LU, "fcvt.d.lu", DXIN64X>; 198 199let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in 200def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">, 201 Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>; 202 203//===----------------------------------------------------------------------===// 204// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 205//===----------------------------------------------------------------------===// 206 207let Predicates = [HasStdExtD] in { 208def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>; 209def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>; 210 211def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 212def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 213def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 214 215// fgt.d/fge.d are recognised by the GNU assembler but the canonical 216// flt.d/fle.d forms will always be printed. Therefore, set a zero weight. 217def : InstAlias<"fgt.d $rd, $rs, $rt", 218 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 219def : InstAlias<"fge.d $rd, $rs, $rt", 220 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 221 222def PseudoFLD : PseudoFloatLoad<"fld", FPR64>; 223def PseudoFSD : PseudoStore<"fsd", FPR64>; 224let usesCustomInserter = 1 in { 225def PseudoQuietFLE_D : PseudoQuietFCMP<FPR64>; 226def PseudoQuietFLT_D : PseudoQuietFCMP<FPR64>; 227} 228} // Predicates = [HasStdExtD] 229 230let Predicates = [HasStdExtZdinx, IsRV64] in { 231def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; 232def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; 233 234def : InstAlias<"fgt.d $rd, $rs, $rt", 235 (FLT_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; 236def : InstAlias<"fge.d $rd, $rs, $rt", 237 (FLE_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; 238} // Predicates = [HasStdExtZdinx, IsRV64] 239 240let Predicates = [HasStdExtZdinx, IsRV32] in { 241def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; 242def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; 243 244def : InstAlias<"fgt.d $rd, $rs, $rt", 245 (FLT_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; 246def : InstAlias<"fge.d $rd, $rs, $rt", 247 (FLE_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; 248} // Predicates = [HasStdExtZdinx, IsRV32] 249 250//===----------------------------------------------------------------------===// 251// Pseudo-instructions and codegen patterns 252//===----------------------------------------------------------------------===// 253 254let Predicates = [HasStdExtD] in { 255 256/// Float conversion operations 257 258// f64 -> f32, f32 -> f64 259def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>; 260def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>; 261 262// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so 263// are defined later. 264 265/// Float arithmetic operations 266 267def : PatFprFprDynFrm<any_fadd, FADD_D, FPR64>; 268def : PatFprFprDynFrm<any_fsub, FSUB_D, FPR64>; 269def : PatFprFprDynFrm<any_fmul, FMUL_D, FPR64>; 270def : PatFprFprDynFrm<any_fdiv, FDIV_D, FPR64>; 271 272def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>; 273 274def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>; 275def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; 276 277def : PatFprFpr<fcopysign, FSGNJ_D, FPR64>; 278def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; 279def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>; 280def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, 281 0b111))>; 282 283// fmadd: rs1 * rs2 + rs3 284def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3), 285 (FMADD_D $rs1, $rs2, $rs3, 0b111)>; 286 287// fmsub: rs1 * rs2 - rs3 288def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)), 289 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 290 291// fnmsub: -rs1 * rs2 + rs3 292def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3), 293 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 294 295// fnmadd: -rs1 * rs2 - rs3 296def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)), 297 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 298 299// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 300def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)), 301 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 302 303// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 304// LLVM's fminnum and fmaxnum. 305// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 306def : PatFprFpr<fminnum, FMIN_D, FPR64>; 307def : PatFprFpr<fmaxnum, FMAX_D, FPR64>; 308 309/// Setcc 310// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for 311// strict versions of those. 312 313// Match non-signaling FEQ_D 314def : PatSetCC<FPR64, any_fsetcc, SETEQ, FEQ_D>; 315def : PatSetCC<FPR64, any_fsetcc, SETOEQ, FEQ_D>; 316def : PatSetCC<FPR64, strict_fsetcc, SETLT, PseudoQuietFLT_D>; 317def : PatSetCC<FPR64, strict_fsetcc, SETOLT, PseudoQuietFLT_D>; 318def : PatSetCC<FPR64, strict_fsetcc, SETLE, PseudoQuietFLE_D>; 319def : PatSetCC<FPR64, strict_fsetcc, SETOLE, PseudoQuietFLE_D>; 320 321// Match signaling FEQ_D 322def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ), 323 (AND (FLE_D $rs1, $rs2), 324 (FLE_D $rs2, $rs1))>; 325def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ), 326 (AND (FLE_D $rs1, $rs2), 327 (FLE_D $rs2, $rs1))>; 328// If both operands are the same, use a single FLE. 329def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ), 330 (FLE_D $rs1, $rs1)>; 331def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ), 332 (FLE_D $rs1, $rs1)>; 333 334def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D>; 335def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D>; 336def : PatSetCC<FPR64, any_fsetccs, SETLE, FLE_D>; 337def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D>; 338 339defm Select_FPR64 : SelectCC_GPR_rrirr<FPR64>; 340 341def PseudoFROUND_D : PseudoFROUND<FPR64>; 342 343/// Loads 344 345defm : LdPat<load, FLD, f64>; 346 347/// Stores 348 349defm : StPat<store, FSD, FPR64, f64>; 350 351/// Pseudo-instructions needed for the soft-float ABI with RV32D 352 353// Moves two GPRs to an FPR. 354let usesCustomInserter = 1 in 355def BuildPairF64Pseudo 356 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2), 357 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>; 358 359// Moves an FPR to two GPRs. 360let usesCustomInserter = 1 in 361def SplitF64Pseudo 362 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src), 363 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>; 364 365} // Predicates = [HasStdExtD] 366 367let Predicates = [HasStdExtD, IsRV32] in { 368 369/// Float constants 370def : Pat<(f64 (fpimm0)), (FCVT_D_W (i32 X0))>; 371def : Pat<(f64 (fpimmneg0)), (FSGNJN_D (FCVT_D_W (i32 X0)), 372 (FCVT_D_W (i32 X0)))>; 373 374// double->[u]int. Round-to-zero must be used. 375def : Pat<(i32 (any_fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, 0b001)>; 376def : Pat<(i32 (any_fp_to_uint FPR64:$rs1)), (FCVT_WU_D FPR64:$rs1, 0b001)>; 377 378// Saturating double->[u]int32. 379def : Pat<(i32 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_W_D $rs1, timm:$frm)>; 380def : Pat<(i32 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_WU_D $rs1, timm:$frm)>; 381 382// float->int32 with current rounding mode. 383def : Pat<(i32 (any_lrint FPR64:$rs1)), (FCVT_W_D $rs1, 0b111)>; 384 385// float->int32 rounded to nearest with ties rounded away from zero. 386def : Pat<(i32 (any_lround FPR64:$rs1)), (FCVT_W_D $rs1, 0b100)>; 387 388// [u]int->double. 389def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1)>; 390def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1)>; 391} // Predicates = [HasStdExtD, IsRV32] 392 393let Predicates = [HasStdExtD, IsRV64] in { 394 395/// Float constants 396def : Pat<(f64 (fpimm0)), (FMV_D_X (i64 X0))>; 397def : Pat<(f64 (fpimmneg0)), (FSGNJN_D (FMV_D_X (i64 X0)), 398 (FMV_D_X (i64 X0)))>; 399 400// Moves (no conversion) 401def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_D_X GPR:$rs1)>; 402def : Pat<(i64 (bitconvert FPR64:$rs1)), (FMV_X_D FPR64:$rs1)>; 403 404// Use target specific isd nodes to help us remember the result is sign 405// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 406// duplicated if it has another user that didn't need the sign_extend. 407def : Pat<(riscv_any_fcvt_w_rv64 FPR64:$rs1, timm:$frm), (FCVT_W_D $rs1, timm:$frm)>; 408def : Pat<(riscv_any_fcvt_wu_rv64 FPR64:$rs1, timm:$frm), (FCVT_WU_D $rs1, timm:$frm)>; 409 410// [u]int32->fp 411def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W $rs1)>; 412def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU $rs1)>; 413 414// Saturating double->[u]int64. 415def : Pat<(i64 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_L_D $rs1, timm:$frm)>; 416def : Pat<(i64 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_LU_D $rs1, timm:$frm)>; 417 418// double->[u]int64. Round-to-zero must be used. 419def : Pat<(i64 (any_fp_to_sint FPR64:$rs1)), (FCVT_L_D FPR64:$rs1, 0b001)>; 420def : Pat<(i64 (any_fp_to_uint FPR64:$rs1)), (FCVT_LU_D FPR64:$rs1, 0b001)>; 421 422// double->int64 with current rounding mode. 423def : Pat<(i64 (any_lrint FPR64:$rs1)), (FCVT_L_D $rs1, 0b111)>; 424def : Pat<(i64 (any_llrint FPR64:$rs1)), (FCVT_L_D $rs1, 0b111)>; 425 426// double->int64 rounded to nearest with ties rounded away from zero. 427def : Pat<(i64 (any_lround FPR64:$rs1)), (FCVT_L_D $rs1, 0b100)>; 428def : Pat<(i64 (any_llround FPR64:$rs1)), (FCVT_L_D $rs1, 0b100)>; 429 430// [u]int64->fp. Match GCC and default to using dynamic rounding mode. 431def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, 0b111)>; 432def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, 0b111)>; 433} // Predicates = [HasStdExtD, IsRV64] 434