1//===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'D', 10// Double-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 19 SDTCisVT<1, i32>, 20 SDTCisSameAs<1, 2>]>; 21def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, 22 SDTCisVT<1, i32>, 23 SDTCisVT<2, f64>]>; 24 25def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>; 26def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>; 27 28def AddrRegImmINX : ComplexPattern<iPTR, 2, "SelectAddrRegImmINX">; 29 30//===----------------------------------------------------------------------===// 31// Operand and SDNode transformation definitions. 32//===----------------------------------------------------------------------===// 33 34// Zdinx 35 36def GPRPairAsFPR : AsmOperandClass { 37 let Name = "GPRPairAsFPR"; 38 let ParserMethod = "parseGPRAsFPR"; 39 let PredicateMethod = "isGPRAsFPR"; 40 let RenderMethod = "addRegOperands"; 41} 42 43def GPRF64AsFPR : AsmOperandClass { 44 let Name = "GPRF64AsFPR"; 45 let PredicateMethod = "isGPRAsFPR"; 46 let ParserMethod = "parseGPRAsFPR"; 47 let RenderMethod = "addRegOperands"; 48} 49 50def FPR64INX : RegisterOperand<GPR> { 51 let ParserMatchClass = GPRF64AsFPR; 52 let DecoderMethod = "DecodeGPRRegisterClass"; 53} 54 55def FPR64IN32X : RegisterOperand<GPRPair> { 56 let ParserMatchClass = GPRPairAsFPR; 57} 58 59def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>; 60 61def ZdinxExt : ExtInfo<"_INX", "RVZfinx", [HasStdExtZdinx, IsRV64], 62 f64, FPR64INX, FPR32INX, FPR64INX, ?>; 63def Zdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", [HasStdExtZdinx, IsRV32], 64 f64, FPR64IN32X, FPR32INX, FPR64IN32X, ?>; 65 66defvar DExts = [DExt, ZdinxExt, Zdinx32Ext]; 67defvar DExtsRV64 = [DExt, ZdinxExt]; 68 69//===----------------------------------------------------------------------===// 70// Instructions 71//===----------------------------------------------------------------------===// 72 73let Predicates = [HasStdExtD] in { 74def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>; 75 76// Operands for stores are in the order srcreg, base, offset rather than 77// reflecting the order these fields are specified in the instruction 78// encoding. 79def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>; 80} // Predicates = [HasStdExtD] 81 82foreach Ext = DExts in { 83 let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in { 84 defm FMADD_D : FPFMA_rrr_frm_m<OPC_MADD, 0b01, "fmadd.d", Ext>; 85 defm FMSUB_D : FPFMA_rrr_frm_m<OPC_MSUB, 0b01, "fmsub.d", Ext>; 86 defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", Ext>; 87 defm FNMADD_D : FPFMA_rrr_frm_m<OPC_NMADD, 0b01, "fnmadd.d", Ext>; 88 } 89 90 let SchedRW = [WriteFAdd64, ReadFAdd64, ReadFAdd64] in { 91 defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", Ext, Commutable=1>; 92 defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", Ext>; 93 } 94 let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in 95 defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", Ext, Commutable=1>; 96 97 let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in 98 defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", Ext>; 99 100 defm FSQRT_D : FPUnaryOp_r_frm_m<0b0101101, 0b00000, Ext, Ext.PrimaryTy, 101 Ext.PrimaryTy, "fsqrt.d">, 102 Sched<[WriteFSqrt64, ReadFSqrt64]>; 103 104 let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64], 105 mayRaiseFPException = 0 in { 106 defm FSGNJ_D : FPALU_rr_m<0b0010001, 0b000, "fsgnj.d", Ext>; 107 defm FSGNJN_D : FPALU_rr_m<0b0010001, 0b001, "fsgnjn.d", Ext>; 108 defm FSGNJX_D : FPALU_rr_m<0b0010001, 0b010, "fsgnjx.d", Ext>; 109 } 110 111 let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in { 112 defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", Ext, Commutable=1>; 113 defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", Ext, Commutable=1>; 114 } 115 116 defm FCVT_S_D : FPUnaryOp_r_frm_m<0b0100000, 0b00001, Ext, Ext.F32Ty, 117 Ext.PrimaryTy, "fcvt.s.d">, 118 Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>; 119 120 defm FCVT_D_S : FPUnaryOp_r_frmlegacy_m<0b0100001, 0b00000, Ext, Ext.PrimaryTy, 121 Ext.F32Ty, "fcvt.d.s">, 122 Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>; 123 124 let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in { 125 defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", Ext, Commutable=1>; 126 defm FLT_D : FPCmp_rr_m<0b1010001, 0b001, "flt.d", Ext>; 127 defm FLE_D : FPCmp_rr_m<0b1010001, 0b000, "fle.d", Ext>; 128 } 129 130 let mayRaiseFPException = 0 in 131 defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy, 132 "fclass.d">, 133 Sched<[WriteFClass64, ReadFClass64]>; 134 135 let IsSignExtendingOpW = 1 in 136 defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, Ext, GPR, Ext.PrimaryTy, 137 "fcvt.w.d">, 138 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; 139 140 let IsSignExtendingOpW = 1 in 141 defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, Ext, GPR, Ext.PrimaryTy, 142 "fcvt.wu.d">, 143 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; 144 145 defm FCVT_D_W : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00000, Ext, Ext.PrimaryTy, GPR, 146 "fcvt.d.w">, 147 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; 148 149 defm FCVT_D_WU : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00001, Ext, Ext.PrimaryTy, GPR, 150 "fcvt.d.wu">, 151 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; 152} // foreach Ext = DExts 153 154foreach Ext = DExtsRV64 in { 155 defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, Ext, GPR, Ext.PrimaryTy, 156 "fcvt.l.d", [IsRV64]>, 157 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; 158 159 defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, Ext, GPR, Ext.PrimaryTy, 160 "fcvt.lu.d", [IsRV64]>, 161 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; 162 163 defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, Ext, Ext.PrimaryTy, GPR, 164 "fcvt.d.l", [IsRV64]>, 165 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; 166 167 defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, Ext, Ext.PrimaryTy, GPR, 168 "fcvt.d.lu", [IsRV64]>, 169 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; 170} // foreach Ext = DExts64 171 172let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in 173def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">, 174 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>; 175 176let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in 177def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">, 178 Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>; 179 180//===----------------------------------------------------------------------===// 181// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 182//===----------------------------------------------------------------------===// 183 184let Predicates = [HasStdExtD] in { 185def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>; 186def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>; 187 188def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 189def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 190def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 191 192// fgt.d/fge.d are recognised by the GNU assembler but the canonical 193// flt.d/fle.d forms will always be printed. Therefore, set a zero weight. 194def : InstAlias<"fgt.d $rd, $rs, $rt", 195 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 196def : InstAlias<"fge.d $rd, $rs, $rt", 197 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 198 199def PseudoFLD : PseudoFloatLoad<"fld", FPR64>; 200def PseudoFSD : PseudoStore<"fsd", FPR64>; 201let usesCustomInserter = 1 in { 202def PseudoQuietFLE_D : PseudoQuietFCMP<FPR64>; 203def PseudoQuietFLT_D : PseudoQuietFCMP<FPR64>; 204} 205} // Predicates = [HasStdExtD] 206 207let Predicates = [HasStdExtZdinx, IsRV64] in { 208def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; 209def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; 210 211def : InstAlias<"fgt.d $rd, $rs, $rt", 212 (FLT_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; 213def : InstAlias<"fge.d $rd, $rs, $rt", 214 (FLE_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; 215let usesCustomInserter = 1 in { 216def PseudoQuietFLE_D_INX : PseudoQuietFCMP<FPR64INX>; 217def PseudoQuietFLT_D_INX : PseudoQuietFCMP<FPR64INX>; 218} 219} // Predicates = [HasStdExtZdinx, IsRV64] 220 221let Predicates = [HasStdExtZdinx, IsRV32] in { 222def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; 223def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; 224 225def : InstAlias<"fgt.d $rd, $rs, $rt", 226 (FLT_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; 227def : InstAlias<"fge.d $rd, $rs, $rt", 228 (FLE_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; 229let usesCustomInserter = 1 in { 230def PseudoQuietFLE_D_IN32X : PseudoQuietFCMP<FPR64IN32X>; 231def PseudoQuietFLT_D_IN32X : PseudoQuietFCMP<FPR64IN32X>; 232} 233} // Predicates = [HasStdExtZdinx, IsRV32] 234 235//===----------------------------------------------------------------------===// 236// Pseudo-instructions and codegen patterns 237//===----------------------------------------------------------------------===// 238 239let Predicates = [HasStdExtD] in { 240 241/// Float conversion operations 242 243// f64 -> f32, f32 -> f64 244def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, FRM_DYN)>; 245def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1, FRM_RNE)>; 246} // Predicates = [HasStdExtD] 247 248let Predicates = [HasStdExtZdinx, IsRV64] in { 249/// Float conversion operations 250 251// f64 -> f32, f32 -> f64 252def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_S_D_INX FPR64INX:$rs1, FRM_DYN)>; 253def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_INX FPR32INX:$rs1, FRM_RNE)>; 254} // Predicates = [HasStdExtZdinx, IsRV64] 255 256let Predicates = [HasStdExtZdinx, IsRV32] in { 257/// Float conversion operations 258 259// f64 -> f32, f32 -> f64 260def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_S_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>; 261def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_IN32X FPR32INX:$rs1, FRM_RNE)>; 262} // Predicates = [HasStdExtZdinx, IsRV32] 263 264// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so 265// are defined later. 266 267/// Float arithmetic operations 268 269foreach Ext = DExts in { 270 defm : PatFprFprDynFrm_m<any_fadd, FADD_D, Ext>; 271 defm : PatFprFprDynFrm_m<any_fsub, FSUB_D, Ext>; 272 defm : PatFprFprDynFrm_m<any_fmul, FMUL_D, Ext>; 273 defm : PatFprFprDynFrm_m<any_fdiv, FDIV_D, Ext>; 274} 275 276let Predicates = [HasStdExtD] in { 277def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, FRM_DYN)>; 278 279def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>; 280def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; 281 282def : Pat<(riscv_fclass FPR64:$rs1), (FCLASS_D $rs1)>; 283 284def : PatFprFpr<fcopysign, FSGNJ_D, FPR64, f64>; 285def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; 286def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2, 287 FRM_RNE))>; 288def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, 289 FRM_DYN))>; 290 291// fmadd: rs1 * rs2 + rs3 292def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3), 293 (FMADD_D $rs1, $rs2, $rs3, FRM_DYN)>; 294 295// fmsub: rs1 * rs2 - rs3 296def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)), 297 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>; 298 299// fnmsub: -rs1 * rs2 + rs3 300def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3), 301 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>; 302 303// fnmadd: -rs1 * rs2 - rs3 304def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)), 305 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>; 306 307// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 308def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)), 309 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>; 310} // Predicates = [HasStdExtD] 311 312let Predicates = [HasStdExtZdinx, IsRV64] in { 313def : Pat<(any_fsqrt FPR64INX:$rs1), (FSQRT_D_INX FPR64INX:$rs1, FRM_DYN)>; 314 315def : Pat<(fneg FPR64INX:$rs1), (FSGNJN_D_INX $rs1, $rs1)>; 316def : Pat<(fabs FPR64INX:$rs1), (FSGNJX_D_INX $rs1, $rs1)>; 317 318def : Pat<(riscv_fclass FPR64INX:$rs1), (FCLASS_D_INX $rs1)>; 319 320def : PatFprFpr<fcopysign, FSGNJ_D_INX, FPR64INX, f64>; 321def : Pat<(fcopysign FPR64INX:$rs1, (fneg FPR64INX:$rs2)), 322 (FSGNJN_D_INX $rs1, $rs2)>; 323def : Pat<(fcopysign FPR64INX:$rs1, FPR32INX:$rs2), 324 (FSGNJ_D_INX $rs1, (FCVT_D_S_INX $rs2, FRM_RNE))>; 325def : Pat<(fcopysign FPR32INX:$rs1, FPR64INX:$rs2), 326 (FSGNJ_S_INX $rs1, (FCVT_S_D_INX $rs2, FRM_DYN))>; 327 328// fmadd: rs1 * rs2 + rs3 329def : Pat<(any_fma FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3), 330 (FMADD_D_INX $rs1, $rs2, $rs3, FRM_DYN)>; 331 332// fmsub: rs1 * rs2 - rs3 333def : Pat<(any_fma FPR64INX:$rs1, FPR64INX:$rs2, (fneg FPR64INX:$rs3)), 334 (FMSUB_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>; 335 336// fnmsub: -rs1 * rs2 + rs3 337def : Pat<(any_fma (fneg FPR64INX:$rs1), FPR64INX:$rs2, FPR64INX:$rs3), 338 (FNMSUB_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>; 339 340// fnmadd: -rs1 * rs2 - rs3 341def : Pat<(any_fma (fneg FPR64INX:$rs1), FPR64INX:$rs2, (fneg FPR64INX:$rs3)), 342 (FNMADD_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>; 343 344// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 345def : Pat<(fneg (any_fma_nsz FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3)), 346 (FNMADD_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>; 347} // Predicates = [HasStdExtZdinx, IsRV64] 348 349let Predicates = [HasStdExtZdinx, IsRV32] in { 350def : Pat<(any_fsqrt FPR64IN32X:$rs1), (FSQRT_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>; 351 352def : Pat<(fneg FPR64IN32X:$rs1), (FSGNJN_D_IN32X $rs1, $rs1)>; 353def : Pat<(fabs FPR64IN32X:$rs1), (FSGNJX_D_IN32X $rs1, $rs1)>; 354 355def : Pat<(riscv_fclass FPR64IN32X:$rs1), (FCLASS_D_IN32X $rs1)>; 356 357def : PatFprFpr<fcopysign, FSGNJ_D_IN32X, FPR64IN32X, f64>; 358def : Pat<(fcopysign FPR64IN32X:$rs1, (fneg FPR64IN32X:$rs2)), 359 (FSGNJN_D_IN32X $rs1, $rs2)>; 360def : Pat<(fcopysign FPR64IN32X:$rs1, FPR32INX:$rs2), 361 (FSGNJ_D_IN32X $rs1, (FCVT_D_S_INX $rs2, FRM_RNE))>; 362def : Pat<(fcopysign FPR32INX:$rs1, FPR64IN32X:$rs2), 363 (FSGNJ_S_INX $rs1, (FCVT_S_D_IN32X $rs2, FRM_DYN))>; 364 365// fmadd: rs1 * rs2 + rs3 366def : Pat<(any_fma FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3), 367 (FMADD_D_IN32X $rs1, $rs2, $rs3, FRM_DYN)>; 368 369// fmsub: rs1 * rs2 - rs3 370def : Pat<(any_fma FPR64IN32X:$rs1, FPR64IN32X:$rs2, (fneg FPR64IN32X:$rs3)), 371 (FMSUB_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>; 372 373// fnmsub: -rs1 * rs2 + rs3 374def : Pat<(any_fma (fneg FPR64IN32X:$rs1), FPR64IN32X:$rs2, FPR64IN32X:$rs3), 375 (FNMSUB_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>; 376 377// fnmadd: -rs1 * rs2 - rs3 378def : Pat<(any_fma (fneg FPR64IN32X:$rs1), FPR64IN32X:$rs2, (fneg FPR64IN32X:$rs3)), 379 (FNMADD_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>; 380 381// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 382def : Pat<(fneg (any_fma_nsz FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3)), 383 (FNMADD_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>; 384} // Predicates = [HasStdExtZdinx, IsRV32] 385 386// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 387// LLVM's fminnum and fmaxnum. 388// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 389foreach Ext = DExts in { 390 defm : PatFprFpr_m<fminnum, FMIN_D, Ext>; 391 defm : PatFprFpr_m<fmaxnum, FMAX_D, Ext>; 392 defm : PatFprFpr_m<riscv_fmin, FMIN_D, Ext>; 393 defm : PatFprFpr_m<riscv_fmax, FMAX_D, Ext>; 394} 395 396/// Setcc 397// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for 398// strict versions of those. 399 400// Match non-signaling FEQ_D 401foreach Ext = DExts in { 402 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_D, Ext>; 403 defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_D, Ext>; 404 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_D, Ext>; 405 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_D, Ext>; 406 defm : PatSetCC_m<strict_fsetcc, SETLE, PseudoQuietFLE_D, Ext>; 407 defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_D, Ext>; 408} 409 410let Predicates = [HasStdExtD] in { 411// Match signaling FEQ_D 412def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)), 413 (AND (FLE_D $rs1, $rs2), 414 (FLE_D $rs2, $rs1))>; 415def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)), 416 (AND (FLE_D $rs1, $rs2), 417 (FLE_D $rs2, $rs1))>; 418// If both operands are the same, use a single FLE. 419def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)), 420 (FLE_D $rs1, $rs1)>; 421def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ)), 422 (FLE_D $rs1, $rs1)>; 423 424def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D, f64>; 425def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D, f64>; 426def : PatSetCC<FPR64, any_fsetccs, SETLE, FLE_D, f64>; 427def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D, f64>; 428} // Predicates = [HasStdExtD] 429 430let Predicates = [HasStdExtZdinx, IsRV64] in { 431// Match signaling FEQ_D 432def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETEQ)), 433 (AND (FLE_D_INX $rs1, $rs2), 434 (FLE_D_INX $rs2, $rs1))>; 435def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETOEQ)), 436 (AND (FLE_D_INX $rs1, $rs2), 437 (FLE_D_INX $rs2, $rs1))>; 438// If both operands are the same, use a single FLE. 439def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETEQ)), 440 (FLE_D_INX $rs1, $rs1)>; 441def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETOEQ)), 442 (FLE_D_INX $rs1, $rs1)>; 443 444def : PatSetCC<FPR64INX, any_fsetccs, SETLT, FLT_D_INX, f64>; 445def : PatSetCC<FPR64INX, any_fsetccs, SETOLT, FLT_D_INX, f64>; 446def : PatSetCC<FPR64INX, any_fsetccs, SETLE, FLE_D_INX, f64>; 447def : PatSetCC<FPR64INX, any_fsetccs, SETOLE, FLE_D_INX, f64>; 448} // Predicates = [HasStdExtZdinx, IsRV64] 449 450let Predicates = [HasStdExtZdinx, IsRV32] in { 451// Match signaling FEQ_D 452def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETEQ)), 453 (AND (FLE_D_IN32X $rs1, $rs2), 454 (FLE_D_IN32X $rs2, $rs1))>; 455def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETOEQ)), 456 (AND (FLE_D_IN32X $rs1, $rs2), 457 (FLE_D_IN32X $rs2, $rs1))>; 458// If both operands are the same, use a single FLE. 459def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETEQ)), 460 (FLE_D_IN32X $rs1, $rs1)>; 461def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETOEQ)), 462 (FLE_D_IN32X $rs1, $rs1)>; 463 464def : PatSetCC<FPR64IN32X, any_fsetccs, SETLT, FLT_D_IN32X, f64>; 465def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLT, FLT_D_IN32X, f64>; 466def : PatSetCC<FPR64IN32X, any_fsetccs, SETLE, FLE_D_IN32X, f64>; 467def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLE, FLE_D_IN32X, f64>; 468} // Predicates = [HasStdExtZdinx, IsRV32] 469 470let Predicates = [HasStdExtD] in { 471defm Select_FPR64 : SelectCC_GPR_rrirr<FPR64, f64>; 472 473def PseudoFROUND_D : PseudoFROUND<FPR64, f64>; 474 475/// Loads 476 477def : LdPat<load, FLD, f64>; 478 479/// Stores 480 481def : StPat<store, FSD, FPR64, f64>; 482 483/// Pseudo-instructions needed for the soft-float ABI with RV32D 484 485// Moves two GPRs to an FPR. 486let usesCustomInserter = 1 in 487def BuildPairF64Pseudo 488 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2), 489 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>; 490 491// Moves an FPR to two GPRs. 492let usesCustomInserter = 1 in 493def SplitF64Pseudo 494 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src), 495 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>; 496 497} // Predicates = [HasStdExtD] 498 499let Predicates = [HasStdExtZdinx, IsRV64] in { 500defm Select_FPR64INX : SelectCC_GPR_rrirr<FPR64INX, f64>; 501 502def PseudoFROUND_D_INX : PseudoFROUND<FPR64INX, f64>; 503 504/// Loads 505def : LdPat<load, LD, f64>; 506 507/// Stores 508def : StPat<store, SD, GPR, f64>; 509} // Predicates = [HasStdExtZdinx, IsRV64] 510 511let Predicates = [HasStdExtZdinx, IsRV32] in { 512defm Select_FPR64IN32X : SelectCC_GPR_rrirr<FPR64IN32X, f64>; 513 514def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64>; 515 516/// Loads 517let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in 518def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>; 519def : Pat<(f64 (load (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12))), 520 (PseudoRV32ZdinxLD GPR:$rs1, simm12:$imm12)>; 521 522/// Stores 523let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in 524def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>; 525def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)), 526 (PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>; 527 528/// Pseudo-instructions needed for the soft-float ABI with RV32D 529 530// Moves two GPRs to an FPR. 531let usesCustomInserter = 1 in 532def BuildPairF64Pseudo_INX 533 : Pseudo<(outs FPR64IN32X:$dst), (ins GPR:$src1, GPR:$src2), 534 [(set FPR64IN32X:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>; 535 536// Moves an FPR to two GPRs. 537let usesCustomInserter = 1 in 538def SplitF64Pseudo_INX 539 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64IN32X:$src), 540 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64IN32X:$src))]>; 541} // Predicates = [HasStdExtZdinx, IsRV32] 542 543let Predicates = [HasStdExtD] in { 544 545// double->[u]int. Round-to-zero must be used. 546def : Pat<(i32 (any_fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, FRM_RTZ)>; 547def : Pat<(i32 (any_fp_to_uint FPR64:$rs1)), (FCVT_WU_D FPR64:$rs1, FRM_RTZ)>; 548 549// Saturating double->[u]int32. 550def : Pat<(i32 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_W_D $rs1, timm:$frm)>; 551def : Pat<(i32 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_WU_D $rs1, timm:$frm)>; 552 553// float->int32 with current rounding mode. 554def : Pat<(i32 (any_lrint FPR64:$rs1)), (FCVT_W_D $rs1, FRM_DYN)>; 555 556// float->int32 rounded to nearest with ties rounded away from zero. 557def : Pat<(i32 (any_lround FPR64:$rs1)), (FCVT_W_D $rs1, FRM_RMM)>; 558 559// [u]int->double. 560def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1, FRM_RNE)>; 561def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1, FRM_RNE)>; 562} // Predicates = [HasStdExtD] 563 564let Predicates = [HasStdExtZdinx, IsRV32] in { 565 566// double->[u]int. Round-to-zero must be used. 567def : Pat<(i32 (any_fp_to_sint FPR64IN32X:$rs1)), (FCVT_W_D_IN32X FPR64IN32X:$rs1, FRM_RTZ)>; 568def : Pat<(i32 (any_fp_to_uint FPR64IN32X:$rs1)), (FCVT_WU_D_IN32X FPR64IN32X:$rs1, FRM_RTZ)>; 569 570// Saturating double->[u]int32. 571def : Pat<(i32 (riscv_fcvt_x FPR64IN32X:$rs1, timm:$frm)), (FCVT_W_D_IN32X $rs1, timm:$frm)>; 572def : Pat<(i32 (riscv_fcvt_xu FPR64IN32X:$rs1, timm:$frm)), (FCVT_WU_D_IN32X $rs1, timm:$frm)>; 573 574// float->int32 with current rounding mode. 575def : Pat<(i32 (any_lrint FPR64IN32X:$rs1)), (FCVT_W_D_IN32X $rs1, FRM_DYN)>; 576 577// float->int32 rounded to nearest with ties rounded away from zero. 578def : Pat<(i32 (any_lround FPR64IN32X:$rs1)), (FCVT_W_D_IN32X $rs1, FRM_RMM)>; 579 580// [u]int->double. 581def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W_IN32X GPR:$rs1, FRM_RNE)>; 582def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU_IN32X GPR:$rs1, FRM_RNE)>; 583} // Predicates = [HasStdExtZdinx, IsRV32] 584 585let Predicates = [HasStdExtD, IsRV64] in { 586 587// Moves (no conversion) 588def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_D_X GPR:$rs1)>; 589def : Pat<(i64 (bitconvert FPR64:$rs1)), (FMV_X_D FPR64:$rs1)>; 590 591// Use target specific isd nodes to help us remember the result is sign 592// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 593// duplicated if it has another user that didn't need the sign_extend. 594def : Pat<(riscv_any_fcvt_w_rv64 FPR64:$rs1, timm:$frm), (FCVT_W_D $rs1, timm:$frm)>; 595def : Pat<(riscv_any_fcvt_wu_rv64 FPR64:$rs1, timm:$frm), (FCVT_WU_D $rs1, timm:$frm)>; 596 597// [u]int32->fp 598def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W $rs1, FRM_RNE)>; 599def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU $rs1, FRM_RNE)>; 600 601// Saturating double->[u]int64. 602def : Pat<(i64 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_L_D $rs1, timm:$frm)>; 603def : Pat<(i64 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_LU_D $rs1, timm:$frm)>; 604 605// double->[u]int64. Round-to-zero must be used. 606def : Pat<(i64 (any_fp_to_sint FPR64:$rs1)), (FCVT_L_D FPR64:$rs1, FRM_RTZ)>; 607def : Pat<(i64 (any_fp_to_uint FPR64:$rs1)), (FCVT_LU_D FPR64:$rs1, FRM_RTZ)>; 608 609// double->int64 with current rounding mode. 610def : Pat<(i64 (any_lrint FPR64:$rs1)), (FCVT_L_D $rs1, FRM_DYN)>; 611def : Pat<(i64 (any_llrint FPR64:$rs1)), (FCVT_L_D $rs1, FRM_DYN)>; 612 613// double->int64 rounded to nearest with ties rounded away from zero. 614def : Pat<(i64 (any_lround FPR64:$rs1)), (FCVT_L_D $rs1, FRM_RMM)>; 615def : Pat<(i64 (any_llround FPR64:$rs1)), (FCVT_L_D $rs1, FRM_RMM)>; 616 617// [u]int64->fp. Match GCC and default to using dynamic rounding mode. 618def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, FRM_DYN)>; 619def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, FRM_DYN)>; 620} // Predicates = [HasStdExtD, IsRV64] 621 622let Predicates = [HasStdExtZdinx, IsRV64] in { 623 624// Moves (no conversion) 625def : Pat<(f64 (bitconvert (i64 GPR:$rs1))), (COPY_TO_REGCLASS GPR:$rs1, GPR)>; 626def : Pat<(i64 (bitconvert (f64 GPR:$rs1))), (COPY_TO_REGCLASS GPR:$rs1, GPR)>; 627 628// Use target specific isd nodes to help us remember the result is sign 629// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 630// duplicated if it has another user that didn't need the sign_extend. 631def : Pat<(riscv_any_fcvt_w_rv64 FPR64INX:$rs1, timm:$frm), (FCVT_W_D_INX $rs1, timm:$frm)>; 632def : Pat<(riscv_any_fcvt_wu_rv64 FPR64INX:$rs1, timm:$frm), (FCVT_WU_D_INX $rs1, timm:$frm)>; 633 634// [u]int32->fp 635def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W_INX $rs1, FRM_RNE)>; 636def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU_INX $rs1, FRM_RNE)>; 637 638// Saturating double->[u]int64. 639def : Pat<(i64 (riscv_fcvt_x FPR64INX:$rs1, timm:$frm)), (FCVT_L_D_INX $rs1, timm:$frm)>; 640def : Pat<(i64 (riscv_fcvt_xu FPR64INX:$rs1, timm:$frm)), (FCVT_LU_D_INX $rs1, timm:$frm)>; 641 642// double->[u]int64. Round-to-zero must be used. 643def : Pat<(i64 (any_fp_to_sint FPR64INX:$rs1)), (FCVT_L_D_INX FPR64INX:$rs1, FRM_RTZ)>; 644def : Pat<(i64 (any_fp_to_uint FPR64INX:$rs1)), (FCVT_LU_D_INX FPR64INX:$rs1, FRM_RTZ)>; 645 646// double->int64 with current rounding mode. 647def : Pat<(i64 (any_lrint FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_DYN)>; 648def : Pat<(i64 (any_llrint FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_DYN)>; 649 650// double->int64 rounded to nearest with ties rounded away from zero. 651def : Pat<(i64 (any_lround FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_RMM)>; 652def : Pat<(i64 (any_llround FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_RMM)>; 653 654// [u]int64->fp. Match GCC and default to using dynamic rounding mode. 655def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L_INX GPR:$rs1, FRM_DYN)>; 656def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU_INX GPR:$rs1, FRM_DYN)>; 657} // Predicates = [HasStdExtZdinx, IsRV64] 658