1//===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'D', 10// Double-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 19 SDTCisVT<1, i32>, 20 SDTCisSameAs<1, 2>]>; 21def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, 22 SDTCisVT<1, i32>, 23 SDTCisVT<2, f64>]>; 24 25def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>; 26def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>; 27 28//===----------------------------------------------------------------------===// 29// Instruction Class Templates 30//===----------------------------------------------------------------------===// 31 32let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 33class FPFMAD_rrr_frm<RISCVOpcode opcode, string opcodestr> 34 : RVInstR4<0b01, opcode, (outs FPR64:$rd), 35 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3), 36 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 37 38class FPFMADDynFrmAlias<FPFMAD_rrr_frm Inst, string OpcodeStr> 39 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 40 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 41 42let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 43class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 44 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd), 45 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">; 46 47let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 48class FPALUD_rr_frm<bits<7> funct7, string opcodestr> 49 : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd), 50 (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr, 51 "$rd, $rs1, $rs2, $funct3">; 52 53class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr> 54 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 55 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>; 56 57let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 58class FPCmpD_rr<bits<3> funct3, string opcodestr> 59 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd), 60 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">; 61 62//===----------------------------------------------------------------------===// 63// Instructions 64//===----------------------------------------------------------------------===// 65 66let Predicates = [HasStdExtD] in { 67 68let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 69def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd), 70 (ins GPR:$rs1, simm12:$imm12), 71 "fld", "$rd, ${imm12}(${rs1})">; 72 73// Operands for stores are in the order srcreg, base, offset rather than 74// reflecting the order these fields are specified in the instruction 75// encoding. 76let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 77def FSD : RVInstS<0b011, OPC_STORE_FP, (outs), 78 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12), 79 "fsd", "$rs2, ${imm12}(${rs1})">; 80 81def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">; 82def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">; 83def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">; 84def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">; 85def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">; 86def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">; 87def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">; 88def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">; 89 90def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">; 91def : FPALUDDynFrmAlias<FADD_D, "fadd.d">; 92def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">; 93def : FPALUDDynFrmAlias<FSUB_D, "fsub.d">; 94def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">; 95def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">; 96def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">; 97def : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">; 98 99def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d"> { 100 let rs2 = 0b00000; 101} 102def : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>; 103 104def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">; 105def FSGNJN_D : FPALUD_rr<0b0010001, 0b001, "fsgnjn.d">; 106def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">; 107def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">; 108def FMAX_D : FPALUD_rr<0b0010101, 0b001, "fmax.d">; 109 110def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d"> { 111 let rs2 = 0b00001; 112} 113def : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>; 114 115def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s"> { 116 let rs2 = 0b00000; 117} 118 119def FEQ_D : FPCmpD_rr<0b010, "feq.d">; 120def FLT_D : FPCmpD_rr<0b001, "flt.d">; 121def FLE_D : FPCmpD_rr<0b000, "fle.d">; 122 123def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d"> { 124 let rs2 = 0b00000; 125} 126 127def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d"> { 128 let rs2 = 0b00000; 129} 130def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>; 131 132def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d"> { 133 let rs2 = 0b00001; 134} 135def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>; 136 137def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> { 138 let rs2 = 0b00000; 139} 140 141def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> { 142 let rs2 = 0b00001; 143} 144} // Predicates = [HasStdExtD] 145 146let Predicates = [HasStdExtD, IsRV64] in { 147def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d"> { 148 let rs2 = 0b00010; 149} 150def : FPUnaryOpDynFrmAlias<FCVT_L_D, "fcvt.l.d", GPR, FPR64>; 151 152def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d"> { 153 let rs2 = 0b00011; 154} 155def : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>; 156 157def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d"> { 158 let rs2 = 0b00000; 159} 160 161def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l"> { 162 let rs2 = 0b00010; 163} 164def : FPUnaryOpDynFrmAlias<FCVT_D_L, "fcvt.d.l", FPR64, GPR>; 165 166def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu"> { 167 let rs2 = 0b00011; 168} 169def : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>; 170 171def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x"> { 172 let rs2 = 0b00000; 173} 174} // Predicates = [HasStdExtD, IsRV64] 175 176//===----------------------------------------------------------------------===// 177// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 178//===----------------------------------------------------------------------===// 179 180let Predicates = [HasStdExtD] in { 181def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>; 182def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>; 183 184def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 185def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 186def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 187 188// fgt.d/fge.d are recognised by the GNU assembler but the canonical 189// flt.d/fle.d forms will always be printed. Therefore, set a zero weight. 190def : InstAlias<"fgt.d $rd, $rs, $rt", 191 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 192def : InstAlias<"fge.d $rd, $rs, $rt", 193 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 194 195def PseudoFLD : PseudoFloatLoad<"fld", FPR64>; 196def PseudoFSD : PseudoStore<"fsd", FPR64>; 197} // Predicates = [HasStdExtD] 198 199//===----------------------------------------------------------------------===// 200// Pseudo-instructions and codegen patterns 201//===----------------------------------------------------------------------===// 202 203class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst> 204 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>; 205 206class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 207 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>; 208 209let Predicates = [HasStdExtD] in { 210 211/// Float conversion operations 212 213// f64 -> f32, f32 -> f64 214def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>; 215def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>; 216 217// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so 218// are defined later. 219 220/// Float arithmetic operations 221 222def : PatFpr64Fpr64DynFrm<fadd, FADD_D>; 223def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>; 224def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>; 225def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>; 226 227def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>; 228 229def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>; 230def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; 231 232def : PatFpr64Fpr64<fcopysign, FSGNJ_D>; 233def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; 234def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>; 235def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, 236 0b111))>; 237 238// fmadd: rs1 * rs2 + rs3 239def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3), 240 (FMADD_D $rs1, $rs2, $rs3, 0b111)>; 241 242// fmsub: rs1 * rs2 - rs3 243def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)), 244 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 245 246// fnmsub: -rs1 * rs2 + rs3 247def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3), 248 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 249 250// fnmadd: -rs1 * rs2 - rs3 251def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)), 252 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 253 254// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the 255// canonical NaN when giving a signaling NaN. This doesn't match the LLVM 256// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the 257// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that 258// matches LLVM's fminnum and fmaxnum 259// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 260def : PatFpr64Fpr64<fminnum, FMIN_D>; 261def : PatFpr64Fpr64<fmaxnum, FMAX_D>; 262 263/// Setcc 264 265def : PatFpr64Fpr64<seteq, FEQ_D>; 266def : PatFpr64Fpr64<setoeq, FEQ_D>; 267def : PatFpr64Fpr64<setlt, FLT_D>; 268def : PatFpr64Fpr64<setolt, FLT_D>; 269def : PatFpr64Fpr64<setle, FLE_D>; 270def : PatFpr64Fpr64<setole, FLE_D>; 271 272// Define pattern expansions for setcc operations which aren't directly 273// handled by a RISC-V instruction and aren't expanded in the SelectionDAG 274// Legalizer. 275 276def : Pat<(seto FPR64:$rs1, FPR64:$rs2), 277 (AND (FEQ_D FPR64:$rs1, FPR64:$rs1), 278 (FEQ_D FPR64:$rs2, FPR64:$rs2))>; 279 280def : Pat<(setuo FPR64:$rs1, FPR64:$rs2), 281 (SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1), 282 (FEQ_D FPR64:$rs2, FPR64:$rs2)), 283 1)>; 284 285def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>; 286 287/// Loads 288 289defm : LdPat<load, FLD>; 290 291/// Stores 292 293defm : StPat<store, FSD, FPR64>; 294 295/// Pseudo-instructions needed for the soft-float ABI with RV32D 296 297// Moves two GPRs to an FPR. 298let usesCustomInserter = 1 in 299def BuildPairF64Pseudo 300 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2), 301 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>; 302 303// Moves an FPR to two GPRs. 304let usesCustomInserter = 1 in 305def SplitF64Pseudo 306 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src), 307 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>; 308 309} // Predicates = [HasStdExtD] 310 311let Predicates = [HasStdExtD, IsRV32] in { 312// double->[u]int. Round-to-zero must be used. 313def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_W_D FPR64:$rs1, 0b001)>; 314def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>; 315 316// [u]int->double. 317def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_W GPR:$rs1)>; 318def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>; 319} // Predicates = [HasStdExtD, IsRV32] 320 321let Predicates = [HasStdExtD, IsRV64] in { 322def : Pat<(bitconvert GPR:$rs1), (FMV_D_X GPR:$rs1)>; 323def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>; 324 325// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe 326// because fpto[u|s]i produce poison if the value can't fit into the target. 327// We match the single case below because fcvt.wu.d sign-extends its result so 328// is cheaper than fcvt.lu.d+sext.w. 329def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR64:$rs1)), i32), 330 (FCVT_WU_D $rs1, 0b001)>; 331 332// [u]int32->fp 333def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_D_W $rs1)>; 334def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_D_WU $rs1)>; 335 336def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_L_D FPR64:$rs1, 0b001)>; 337def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_LU_D FPR64:$rs1, 0b001)>; 338 339// [u]int64->fp. Match GCC and default to using dynamic rounding mode. 340def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_L GPR:$rs1, 0b111)>; 341def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_LU GPR:$rs1, 0b111)>; 342} // Predicates = [HasStdExtD, IsRV64] 343