1//===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'D', 10// Double-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 19 SDTCisVT<1, i32>, 20 SDTCisSameAs<1, 2>]>; 21def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, 22 SDTCisVT<1, i32>, 23 SDTCisVT<2, f64>]>; 24 25def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>; 26def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>; 27 28//===----------------------------------------------------------------------===// 29// Instruction Class Templates 30//===----------------------------------------------------------------------===// 31 32let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 33class FPFMAD_rrr_frm<RISCVOpcode opcode, string opcodestr> 34 : RVInstR4Frm<0b01, opcode, (outs FPR64:$rd), 35 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3), 36 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 37 38class FPFMADDynFrmAlias<FPFMAD_rrr_frm Inst, string OpcodeStr> 39 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 40 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 41 42let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 43class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 44 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd), 45 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">; 46 47let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 48class FPALUD_rr_frm<bits<7> funct7, string opcodestr> 49 : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd), 50 (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr, 51 "$rd, $rs1, $rs2, $funct3">; 52 53class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr> 54 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 55 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>; 56 57let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 58class FPCmpD_rr<bits<3> funct3, string opcodestr> 59 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd), 60 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">, 61 Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>; 62 63//===----------------------------------------------------------------------===// 64// Instructions 65//===----------------------------------------------------------------------===// 66 67let Predicates = [HasStdExtD] in { 68 69let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 70def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd), 71 (ins GPR:$rs1, simm12:$imm12), 72 "fld", "$rd, ${imm12}(${rs1})">, 73 Sched<[WriteFLD64, ReadFMemBase]>; 74 75// Operands for stores are in the order srcreg, base, offset rather than 76// reflecting the order these fields are specified in the instruction 77// encoding. 78let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 79def FSD : RVInstS<0b011, OPC_STORE_FP, (outs), 80 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12), 81 "fsd", "$rs2, ${imm12}(${rs1})">, 82 Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>; 83 84def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">, 85 Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>; 86def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">; 87def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">, 88 Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>; 89def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">; 90def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">, 91 Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>; 92def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">; 93def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">, 94 Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>; 95def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">; 96 97def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">, 98 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>; 99def : FPALUDDynFrmAlias<FADD_D, "fadd.d">; 100def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">, 101 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>; 102def : FPALUDDynFrmAlias<FSUB_D, "fsub.d">; 103def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">, 104 Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>; 105def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">; 106def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">, 107 Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>; 108def : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">; 109 110def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">, 111 Sched<[WriteFSqrt64, ReadFSqrt64]> { 112 let rs2 = 0b00000; 113} 114def : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>; 115 116def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">, 117 Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>; 118def FSGNJN_D : FPALUD_rr<0b0010001, 0b001, "fsgnjn.d">, 119 Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>; 120def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">, 121 Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>; 122def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">, 123 Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>; 124def FMAX_D : FPALUD_rr<0b0010101, 0b001, "fmax.d">, 125 Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>; 126 127def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d">, 128 Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]> { 129 let rs2 = 0b00001; 130} 131def : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>; 132 133def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s">, 134 Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]> { 135 let rs2 = 0b00000; 136} 137 138def FEQ_D : FPCmpD_rr<0b010, "feq.d">; 139def FLT_D : FPCmpD_rr<0b001, "flt.d">; 140def FLE_D : FPCmpD_rr<0b000, "fle.d">; 141 142def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">, 143 Sched<[WriteFClass64, ReadFClass64]> { 144 let rs2 = 0b00000; 145} 146 147def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">, 148 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> { 149 let rs2 = 0b00000; 150} 151def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>; 152 153def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">, 154 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> { 155 let rs2 = 0b00001; 156} 157def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>; 158 159def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">, 160 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> { 161 let rs2 = 0b00000; 162} 163 164def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">, 165 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> { 166 let rs2 = 0b00001; 167} 168} // Predicates = [HasStdExtD] 169 170let Predicates = [HasStdExtD, IsRV64] in { 171def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d">, 172 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> { 173 let rs2 = 0b00010; 174} 175def : FPUnaryOpDynFrmAlias<FCVT_L_D, "fcvt.l.d", GPR, FPR64>; 176 177def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d">, 178 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> { 179 let rs2 = 0b00011; 180} 181def : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>; 182 183def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d">, 184 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]> { 185 let rs2 = 0b00000; 186} 187 188def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l">, 189 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> { 190 let rs2 = 0b00010; 191} 192def : FPUnaryOpDynFrmAlias<FCVT_D_L, "fcvt.d.l", FPR64, GPR>; 193 194def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu">, 195 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> { 196 let rs2 = 0b00011; 197} 198def : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>; 199 200def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x">, 201 Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]> { 202 let rs2 = 0b00000; 203} 204} // Predicates = [HasStdExtD, IsRV64] 205 206//===----------------------------------------------------------------------===// 207// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 208//===----------------------------------------------------------------------===// 209 210let Predicates = [HasStdExtD] in { 211def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>; 212def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>; 213 214def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 215def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 216def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 217 218// fgt.d/fge.d are recognised by the GNU assembler but the canonical 219// flt.d/fle.d forms will always be printed. Therefore, set a zero weight. 220def : InstAlias<"fgt.d $rd, $rs, $rt", 221 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 222def : InstAlias<"fge.d $rd, $rs, $rt", 223 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 224 225def PseudoFLD : PseudoFloatLoad<"fld", FPR64>; 226def PseudoFSD : PseudoStore<"fsd", FPR64>; 227} // Predicates = [HasStdExtD] 228 229//===----------------------------------------------------------------------===// 230// Pseudo-instructions and codegen patterns 231//===----------------------------------------------------------------------===// 232 233class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst> 234 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>; 235 236class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 237 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>; 238 239let Predicates = [HasStdExtD] in { 240 241/// Float conversion operations 242 243// f64 -> f32, f32 -> f64 244def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>; 245def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>; 246 247// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so 248// are defined later. 249 250/// Float arithmetic operations 251 252def : PatFpr64Fpr64DynFrm<fadd, FADD_D>; 253def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>; 254def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>; 255def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>; 256 257def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>; 258 259def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>; 260def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; 261 262def : PatFpr64Fpr64<fcopysign, FSGNJ_D>; 263def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; 264def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>; 265def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, 266 0b111))>; 267 268// fmadd: rs1 * rs2 + rs3 269def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3), 270 (FMADD_D $rs1, $rs2, $rs3, 0b111)>; 271 272// fmsub: rs1 * rs2 - rs3 273def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)), 274 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 275 276// fnmsub: -rs1 * rs2 + rs3 277def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3), 278 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 279 280// fnmadd: -rs1 * rs2 - rs3 281def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)), 282 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 283 284// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 285// LLVM's fminnum and fmaxnum. 286// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 287def : PatFpr64Fpr64<fminnum, FMIN_D>; 288def : PatFpr64Fpr64<fmaxnum, FMAX_D>; 289 290/// Setcc 291 292def : PatFpr64Fpr64<seteq, FEQ_D>; 293def : PatFpr64Fpr64<setoeq, FEQ_D>; 294def : PatFpr64Fpr64<setlt, FLT_D>; 295def : PatFpr64Fpr64<setolt, FLT_D>; 296def : PatFpr64Fpr64<setle, FLE_D>; 297def : PatFpr64Fpr64<setole, FLE_D>; 298 299def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>; 300 301/// Loads 302 303defm : LdPat<load, FLD, f64>; 304 305/// Stores 306 307defm : StPat<store, FSD, FPR64, f64>; 308 309/// Pseudo-instructions needed for the soft-float ABI with RV32D 310 311// Moves two GPRs to an FPR. 312let usesCustomInserter = 1 in 313def BuildPairF64Pseudo 314 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2), 315 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>; 316 317// Moves an FPR to two GPRs. 318let usesCustomInserter = 1 in 319def SplitF64Pseudo 320 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src), 321 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>; 322 323} // Predicates = [HasStdExtD] 324 325let Predicates = [HasStdExtD, IsRV32] in { 326 327/// Float constants 328def : Pat<(f64 (fpimm0)), (FCVT_D_W (i32 X0))>; 329 330// double->[u]int. Round-to-zero must be used. 331def : Pat<(i32 (fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, 0b001)>; 332def : Pat<(i32 (fp_to_uint FPR64:$rs1)), (FCVT_WU_D FPR64:$rs1, 0b001)>; 333 334// float->int32 with current rounding mode. 335def : Pat<(i32 (lrint FPR64:$rs1)), (FCVT_W_D $rs1, 0b111)>; 336 337// float->int32 rounded to nearest with ties rounded away from zero. 338def : Pat<(i32 (lround FPR64:$rs1)), (FCVT_W_D $rs1, 0b100)>; 339 340// [u]int->double. 341def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1)>; 342def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1)>; 343} // Predicates = [HasStdExtD, IsRV32] 344 345let Predicates = [HasStdExtD, IsRV64] in { 346 347/// Float constants 348def : Pat<(f64 (fpimm0)), (FMV_D_X (i64 X0))>; 349 350// Moves (no conversion) 351def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_D_X GPR:$rs1)>; 352def : Pat<(i64 (bitconvert FPR64:$rs1)), (FMV_X_D FPR64:$rs1)>; 353 354// Use target specific isd nodes to help us remember the result is sign 355// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 356// duplicated if it has another user that didn't need the sign_extend. 357def : Pat<(riscv_fcvt_w_rv64 FPR64:$rs1), (FCVT_W_D $rs1, 0b001)>; 358def : Pat<(riscv_fcvt_wu_rv64 FPR64:$rs1), (FCVT_WU_D $rs1, 0b001)>; 359 360// [u]int32->fp 361def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W $rs1)>; 362def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU $rs1)>; 363 364// double->[u]int64. Round-to-zero must be used. 365def : Pat<(i64 (fp_to_sint FPR64:$rs1)), (FCVT_L_D FPR64:$rs1, 0b001)>; 366def : Pat<(i64 (fp_to_uint FPR64:$rs1)), (FCVT_LU_D FPR64:$rs1, 0b001)>; 367 368// double->int64 with current rounding mode. 369def : Pat<(i64 (lrint FPR64:$rs1)), (FCVT_L_D $rs1, 0b111)>; 370def : Pat<(i64 (llrint FPR64:$rs1)), (FCVT_L_D $rs1, 0b111)>; 371 372// double->int64 rounded to nearest with ties rounded away from zero. 373def : Pat<(i64 (lround FPR64:$rs1)), (FCVT_L_D $rs1, 0b100)>; 374def : Pat<(i64 (llround FPR64:$rs1)), (FCVT_L_D $rs1, 0b100)>; 375 376// [u]int64->fp. Match GCC and default to using dynamic rounding mode. 377def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, 0b111)>; 378def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, 0b111)>; 379} // Predicates = [HasStdExtD, IsRV64] 380