1//===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// RISC-V specific DAG Nodes. 15//===----------------------------------------------------------------------===// 16 17// Target-independent type requirements, but with target-specific formats. 18def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, 19 SDTCisVT<1, i32>]>; 20def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 21 SDTCisVT<1, i32>]>; 22 23// Target-dependent type requirements. 24def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>; 25def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>, 26 SDTCisSameAs<0, 4>, 27 SDTCisSameAs<4, 5>]>; 28 29// Target-independent nodes, but with target-specific formats. 30def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, 31 [SDNPHasChain, SDNPOutGlue]>; 32def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd, 33 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 34 35// Target-dependent nodes. 36def riscv_call : SDNode<"RISCVISD::CALL", SDT_RISCVCall, 37 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 38 SDNPVariadic]>; 39def riscv_ret_flag : SDNode<"RISCVISD::RET_FLAG", SDTNone, 40 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 41def riscv_uret_flag : SDNode<"RISCVISD::URET_FLAG", SDTNone, 42 [SDNPHasChain, SDNPOptInGlue]>; 43def riscv_sret_flag : SDNode<"RISCVISD::SRET_FLAG", SDTNone, 44 [SDNPHasChain, SDNPOptInGlue]>; 45def riscv_mret_flag : SDNode<"RISCVISD::MRET_FLAG", SDTNone, 46 [SDNPHasChain, SDNPOptInGlue]>; 47def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC, 48 [SDNPInGlue]>; 49def riscv_tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall, 50 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 51 SDNPVariadic]>; 52def riscv_sllw : SDNode<"RISCVISD::SLLW", SDTIntShiftOp>; 53def riscv_sraw : SDNode<"RISCVISD::SRAW", SDTIntShiftOp>; 54def riscv_srlw : SDNode<"RISCVISD::SRLW", SDTIntShiftOp>; 55 56//===----------------------------------------------------------------------===// 57// Operand and SDNode transformation definitions. 58//===----------------------------------------------------------------------===// 59 60class ImmXLenAsmOperand<string prefix, string suffix = ""> : AsmOperandClass { 61 let Name = prefix # "ImmXLen" # suffix; 62 let RenderMethod = "addImmOperands"; 63 let DiagnosticType = !strconcat("Invalid", Name); 64} 65 66class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass { 67 let Name = prefix # "Imm" # width # suffix; 68 let RenderMethod = "addImmOperands"; 69 let DiagnosticType = !strconcat("Invalid", Name); 70} 71 72def ImmZeroAsmOperand : AsmOperandClass { 73 let Name = "ImmZero"; 74 let RenderMethod = "addImmOperands"; 75 let DiagnosticType = !strconcat("Invalid", Name); 76} 77 78class SImmAsmOperand<int width, string suffix = ""> 79 : ImmAsmOperand<"S", width, suffix> { 80} 81 82class UImmAsmOperand<int width, string suffix = ""> 83 : ImmAsmOperand<"U", width, suffix> { 84} 85 86def FenceArg : AsmOperandClass { 87 let Name = "FenceArg"; 88 let RenderMethod = "addFenceArgOperands"; 89 let DiagnosticType = "InvalidFenceArg"; 90} 91 92def fencearg : Operand<XLenVT> { 93 let ParserMatchClass = FenceArg; 94 let PrintMethod = "printFenceArg"; 95 let DecoderMethod = "decodeUImmOperand<4>"; 96 let OperandType = "OPERAND_UIMM4"; 97 let OperandNamespace = "RISCVOp"; 98} 99 100def UImmLog2XLenAsmOperand : AsmOperandClass { 101 let Name = "UImmLog2XLen"; 102 let RenderMethod = "addImmOperands"; 103 let DiagnosticType = "InvalidUImmLog2XLen"; 104} 105 106def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{ 107 if (Subtarget->is64Bit()) 108 return isUInt<6>(Imm); 109 return isUInt<5>(Imm); 110}]> { 111 let ParserMatchClass = UImmLog2XLenAsmOperand; 112 // TODO: should ensure invalid shamt is rejected when decoding. 113 let DecoderMethod = "decodeUImmOperand<6>"; 114 let MCOperandPredicate = [{ 115 int64_t Imm; 116 if (!MCOp.evaluateAsConstantImm(Imm)) 117 return false; 118 if (STI.getTargetTriple().isArch64Bit()) 119 return isUInt<6>(Imm); 120 return isUInt<5>(Imm); 121 }]; 122 let OperandType = "OPERAND_UIMMLOG2XLEN"; 123 let OperandNamespace = "RISCVOp"; 124} 125 126def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> { 127 let ParserMatchClass = UImmAsmOperand<5>; 128 let DecoderMethod = "decodeUImmOperand<5>"; 129 let OperandType = "OPERAND_UIMM5"; 130 let OperandNamespace = "RISCVOp"; 131} 132 133def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> { 134 let ParserMatchClass = SImmAsmOperand<12>; 135 let EncoderMethod = "getImmOpValue"; 136 let DecoderMethod = "decodeSImmOperand<12>"; 137 let MCOperandPredicate = [{ 138 int64_t Imm; 139 if (MCOp.evaluateAsConstantImm(Imm)) 140 return isInt<12>(Imm); 141 return MCOp.isBareSymbolRef(); 142 }]; 143 let OperandType = "OPERAND_SIMM12"; 144 let OperandNamespace = "RISCVOp"; 145} 146 147// A 13-bit signed immediate where the least significant bit is zero. 148def simm13_lsb0 : Operand<OtherVT> { 149 let ParserMatchClass = SImmAsmOperand<13, "Lsb0">; 150 let EncoderMethod = "getImmOpValueAsr1"; 151 let DecoderMethod = "decodeSImmOperandAndLsl1<13>"; 152 let MCOperandPredicate = [{ 153 int64_t Imm; 154 if (MCOp.evaluateAsConstantImm(Imm)) 155 return isShiftedInt<12, 1>(Imm); 156 return MCOp.isBareSymbolRef(); 157 }]; 158 let OperandType = "OPERAND_SIMM13_LSB0"; 159 let OperandNamespace = "RISCVOp"; 160} 161 162class UImm20Operand : Operand<XLenVT> { 163 let EncoderMethod = "getImmOpValue"; 164 let DecoderMethod = "decodeUImmOperand<20>"; 165 let MCOperandPredicate = [{ 166 int64_t Imm; 167 if (MCOp.evaluateAsConstantImm(Imm)) 168 return isUInt<20>(Imm); 169 return MCOp.isBareSymbolRef(); 170 }]; 171 let OperandType = "OPERAND_UIMM20"; 172 let OperandNamespace = "RISCVOp"; 173} 174 175def uimm20_lui : UImm20Operand { 176 let ParserMatchClass = UImmAsmOperand<20, "LUI">; 177} 178def uimm20_auipc : UImm20Operand { 179 let ParserMatchClass = UImmAsmOperand<20, "AUIPC">; 180} 181 182def Simm21Lsb0JALAsmOperand : SImmAsmOperand<21, "Lsb0JAL"> { 183 let ParserMethod = "parseJALOffset"; 184} 185 186// A 21-bit signed immediate where the least significant bit is zero. 187def simm21_lsb0_jal : Operand<OtherVT> { 188 let ParserMatchClass = Simm21Lsb0JALAsmOperand; 189 let EncoderMethod = "getImmOpValueAsr1"; 190 let DecoderMethod = "decodeSImmOperandAndLsl1<21>"; 191 let MCOperandPredicate = [{ 192 int64_t Imm; 193 if (MCOp.evaluateAsConstantImm(Imm)) 194 return isShiftedInt<20, 1>(Imm); 195 return MCOp.isBareSymbolRef(); 196 }]; 197 let OperandType = "OPERAND_SIMM21_LSB0"; 198 let OperandNamespace = "RISCVOp"; 199} 200 201def BareSymbol : AsmOperandClass { 202 let Name = "BareSymbol"; 203 let RenderMethod = "addImmOperands"; 204 let DiagnosticType = "InvalidBareSymbol"; 205 let ParserMethod = "parseBareSymbol"; 206} 207 208// A bare symbol. 209def bare_symbol : Operand<XLenVT> { 210 let ParserMatchClass = BareSymbol; 211} 212 213def CallSymbol : AsmOperandClass { 214 let Name = "CallSymbol"; 215 let RenderMethod = "addImmOperands"; 216 let DiagnosticType = "InvalidCallSymbol"; 217 let ParserMethod = "parseCallSymbol"; 218} 219 220// A bare symbol used in call/tail only. 221def call_symbol : Operand<XLenVT> { 222 let ParserMatchClass = CallSymbol; 223} 224 225def TPRelAddSymbol : AsmOperandClass { 226 let Name = "TPRelAddSymbol"; 227 let RenderMethod = "addImmOperands"; 228 let DiagnosticType = "InvalidTPRelAddSymbol"; 229 let ParserMethod = "parseOperandWithModifier"; 230} 231 232// A bare symbol with the %tprel_add variant. 233def tprel_add_symbol : Operand<XLenVT> { 234 let ParserMatchClass = TPRelAddSymbol; 235} 236 237def CSRSystemRegister : AsmOperandClass { 238 let Name = "CSRSystemRegister"; 239 let ParserMethod = "parseCSRSystemRegister"; 240 let DiagnosticType = "InvalidCSRSystemRegister"; 241} 242 243def csr_sysreg : Operand<XLenVT> { 244 let ParserMatchClass = CSRSystemRegister; 245 let PrintMethod = "printCSRSystemRegister"; 246 let DecoderMethod = "decodeUImmOperand<12>"; 247 let OperandType = "OPERAND_UIMM12"; 248 let OperandNamespace = "RISCVOp"; 249} 250 251// A parameterized register class alternative to i32imm/i64imm from Target.td. 252def ixlenimm : Operand<XLenVT>; 253 254def ixlenimm_li : Operand<XLenVT> { 255 let ParserMatchClass = ImmXLenAsmOperand<"", "LI">; 256} 257 258// Standalone (codegen-only) immleaf patterns. 259def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>; 260def simm32hi20 : ImmLeaf<XLenVT, [{return isShiftedInt<20, 12>(Imm);}]>; 261// A mask value that won't affect significant shift bits. 262def immbottomxlenset : ImmLeaf<XLenVT, [{ 263 if (Subtarget->is64Bit()) 264 return countTrailingOnes<uint64_t>(Imm) >= 6; 265 return countTrailingOnes<uint64_t>(Imm) >= 5; 266}]>; 267 268// Addressing modes. 269// Necessary because a frameindex can't be matched directly in a pattern. 270def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>; 271 272// Extract least significant 12 bits from an immediate value and sign extend 273// them. 274def LO12Sext : SDNodeXForm<imm, [{ 275 return CurDAG->getTargetConstant(SignExtend64<12>(N->getZExtValue()), 276 SDLoc(N), N->getValueType(0)); 277}]>; 278 279// Extract the most significant 20 bits from an immediate value. Add 1 if bit 280// 11 is 1, to compensate for the low 12 bits in the matching immediate addi 281// or ld/st being negative. 282def HI20 : SDNodeXForm<imm, [{ 283 return CurDAG->getTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff, 284 SDLoc(N), N->getValueType(0)); 285}]>; 286 287//===----------------------------------------------------------------------===// 288// Instruction Formats 289//===----------------------------------------------------------------------===// 290 291include "RISCVInstrFormats.td" 292 293//===----------------------------------------------------------------------===// 294// Instruction Class Templates 295//===----------------------------------------------------------------------===// 296 297let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 298class BranchCC_rri<bits<3> funct3, string opcodestr> 299 : RVInstB<funct3, OPC_BRANCH, (outs), 300 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12), 301 opcodestr, "$rs1, $rs2, $imm12"> { 302 let isBranch = 1; 303 let isTerminator = 1; 304} 305 306let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 307class Load_ri<bits<3> funct3, string opcodestr> 308 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), 309 opcodestr, "$rd, ${imm12}(${rs1})">; 310 311// Operands for stores are in the order srcreg, base, offset rather than 312// reflecting the order these fields are specified in the instruction 313// encoding. 314let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 315class Store_rri<bits<3> funct3, string opcodestr> 316 : RVInstS<funct3, OPC_STORE, (outs), 317 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12), 318 opcodestr, "$rs2, ${imm12}(${rs1})">; 319 320let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 321class ALU_ri<bits<3> funct3, string opcodestr> 322 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), 323 opcodestr, "$rd, $rs1, $imm12">; 324 325let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 326class Shift_ri<bit arithshift, bits<3> funct3, string opcodestr> 327 : RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd), 328 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr, 329 "$rd, $rs1, $shamt">; 330 331let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 332class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 333 : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), 334 opcodestr, "$rd, $rs1, $rs2">; 335 336let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 337class CSR_ir<bits<3> funct3, string opcodestr> 338 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1), 339 opcodestr, "$rd, $imm12, $rs1">; 340 341let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 342class CSR_ii<bits<3> funct3, string opcodestr> 343 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), 344 (ins csr_sysreg:$imm12, uimm5:$rs1), 345 opcodestr, "$rd, $imm12, $rs1">; 346 347let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 348class ShiftW_ri<bit arithshift, bits<3> funct3, string opcodestr> 349 : RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd), 350 (ins GPR:$rs1, uimm5:$shamt), opcodestr, 351 "$rd, $rs1, $shamt">; 352 353let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 354class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 355 : RVInstR<funct7, funct3, OPC_OP_32, (outs GPR:$rd), 356 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">; 357 358let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 359class Priv<string opcodestr, bits<7> funct7> 360 : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2), 361 opcodestr, "">; 362 363//===----------------------------------------------------------------------===// 364// Instructions 365//===----------------------------------------------------------------------===// 366 367let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 368let isReMaterializable = 1, isAsCheapAsAMove = 1 in 369def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20), 370 "lui", "$rd, $imm20">; 371 372def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20), 373 "auipc", "$rd, $imm20">; 374 375let isCall = 1 in 376def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20), 377 "jal", "$rd, $imm20">; 378 379let isCall = 1 in 380def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd), 381 (ins GPR:$rs1, simm12:$imm12), 382 "jalr", "$rd, ${imm12}(${rs1})">; 383} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 384 385def BEQ : BranchCC_rri<0b000, "beq">; 386def BNE : BranchCC_rri<0b001, "bne">; 387def BLT : BranchCC_rri<0b100, "blt">; 388def BGE : BranchCC_rri<0b101, "bge">; 389def BLTU : BranchCC_rri<0b110, "bltu">; 390def BGEU : BranchCC_rri<0b111, "bgeu">; 391 392def LB : Load_ri<0b000, "lb">; 393def LH : Load_ri<0b001, "lh">; 394def LW : Load_ri<0b010, "lw">; 395def LBU : Load_ri<0b100, "lbu">; 396def LHU : Load_ri<0b101, "lhu">; 397 398def SB : Store_rri<0b000, "sb">; 399def SH : Store_rri<0b001, "sh">; 400def SW : Store_rri<0b010, "sw">; 401 402// ADDI isn't always rematerializable, but isReMaterializable will be used as 403// a hint which is verified in isReallyTriviallyReMaterializable. 404let isReMaterializable = 1, isAsCheapAsAMove = 1 in 405def ADDI : ALU_ri<0b000, "addi">; 406 407def SLTI : ALU_ri<0b010, "slti">; 408def SLTIU : ALU_ri<0b011, "sltiu">; 409 410let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 411def XORI : ALU_ri<0b100, "xori">; 412def ORI : ALU_ri<0b110, "ori">; 413} 414 415def ANDI : ALU_ri<0b111, "andi">; 416 417def SLLI : Shift_ri<0, 0b001, "slli">; 418def SRLI : Shift_ri<0, 0b101, "srli">; 419def SRAI : Shift_ri<1, 0b101, "srai">; 420 421def ADD : ALU_rr<0b0000000, 0b000, "add">; 422def SUB : ALU_rr<0b0100000, 0b000, "sub">; 423def SLL : ALU_rr<0b0000000, 0b001, "sll">; 424def SLT : ALU_rr<0b0000000, 0b010, "slt">; 425def SLTU : ALU_rr<0b0000000, 0b011, "sltu">; 426def XOR : ALU_rr<0b0000000, 0b100, "xor">; 427def SRL : ALU_rr<0b0000000, 0b101, "srl">; 428def SRA : ALU_rr<0b0100000, 0b101, "sra">; 429def OR : ALU_rr<0b0000000, 0b110, "or">; 430def AND : ALU_rr<0b0000000, 0b111, "and">; 431 432let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { 433def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs), 434 (ins fencearg:$pred, fencearg:$succ), 435 "fence", "$pred, $succ"> { 436 bits<4> pred; 437 bits<4> succ; 438 439 let rs1 = 0; 440 let rd = 0; 441 let imm12 = {0b0000,pred,succ}; 442} 443 444def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", ""> { 445 let rs1 = 0; 446 let rd = 0; 447 let imm12 = {0b1000,0b0011,0b0011}; 448} 449 450def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", ""> { 451 let rs1 = 0; 452 let rd = 0; 453 let imm12 = 0; 454} 455 456def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", ""> { 457 let rs1 = 0; 458 let rd = 0; 459 let imm12 = 0; 460} 461 462def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", ""> { 463 let rs1 = 0; 464 let rd = 0; 465 let imm12 = 1; 466} 467 468// This is a de facto standard (as set by GNU binutils) 32-bit unimplemented 469// instruction (i.e., it should always trap, if your implementation has invalid 470// instruction traps). 471def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", ""> { 472 let rs1 = 0; 473 let rd = 0; 474 let imm12 = 0b110000000000; 475} 476} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 477 478def CSRRW : CSR_ir<0b001, "csrrw">; 479def CSRRS : CSR_ir<0b010, "csrrs">; 480def CSRRC : CSR_ir<0b011, "csrrc">; 481 482def CSRRWI : CSR_ii<0b101, "csrrwi">; 483def CSRRSI : CSR_ii<0b110, "csrrsi">; 484def CSRRCI : CSR_ii<0b111, "csrrci">; 485 486/// RV64I instructions 487 488let Predicates = [IsRV64] in { 489def LWU : Load_ri<0b110, "lwu">; 490def LD : Load_ri<0b011, "ld">; 491def SD : Store_rri<0b011, "sd">; 492 493let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 494def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd), 495 (ins GPR:$rs1, simm12:$imm12), 496 "addiw", "$rd, $rs1, $imm12">; 497 498def SLLIW : ShiftW_ri<0, 0b001, "slliw">; 499def SRLIW : ShiftW_ri<0, 0b101, "srliw">; 500def SRAIW : ShiftW_ri<1, 0b101, "sraiw">; 501 502def ADDW : ALUW_rr<0b0000000, 0b000, "addw">; 503def SUBW : ALUW_rr<0b0100000, 0b000, "subw">; 504def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">; 505def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">; 506def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">; 507} // Predicates = [IsRV64] 508 509//===----------------------------------------------------------------------===// 510// Privileged instructions 511//===----------------------------------------------------------------------===// 512 513let isBarrier = 1, isReturn = 1, isTerminator = 1 in { 514def URET : Priv<"uret", 0b0000000> { 515 let rd = 0; 516 let rs1 = 0; 517 let rs2 = 0b00010; 518} 519 520def SRET : Priv<"sret", 0b0001000> { 521 let rd = 0; 522 let rs1 = 0; 523 let rs2 = 0b00010; 524} 525 526def MRET : Priv<"mret", 0b0011000> { 527 let rd = 0; 528 let rs1 = 0; 529 let rs2 = 0b00010; 530} 531} // isBarrier = 1, isReturn = 1, isTerminator = 1 532 533def WFI : Priv<"wfi", 0b0001000> { 534 let rd = 0; 535 let rs1 = 0; 536 let rs2 = 0b00101; 537} 538 539let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 540def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs), 541 (ins GPR:$rs1, GPR:$rs2), 542 "sfence.vma", "$rs1, $rs2"> { 543 let rd = 0; 544} 545 546//===----------------------------------------------------------------------===// 547// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 548//===----------------------------------------------------------------------===// 549 550def : InstAlias<"nop", (ADDI X0, X0, 0)>; 551 552// Note that the size is 32 because up to 8 32-bit instructions are needed to 553// generate an arbitrary 64-bit immediate. However, the size does not really 554// matter since PseudoLI is currently only used in the AsmParser where it gets 555// expanded to real instructions immediately. 556let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 32, 557 isCodeGenOnly = 0, isAsmParserOnly = 1 in 558def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm_li:$imm), [], 559 "li", "$rd, $imm">; 560 561def PseudoLB : PseudoLoad<"lb">; 562def PseudoLBU : PseudoLoad<"lbu">; 563def PseudoLH : PseudoLoad<"lh">; 564def PseudoLHU : PseudoLoad<"lhu">; 565def PseudoLW : PseudoLoad<"lw">; 566 567def PseudoSB : PseudoStore<"sb">; 568def PseudoSH : PseudoStore<"sh">; 569def PseudoSW : PseudoStore<"sw">; 570 571let Predicates = [IsRV64] in { 572def PseudoLWU : PseudoLoad<"lwu">; 573def PseudoLD : PseudoLoad<"ld">; 574def PseudoSD : PseudoStore<"sd">; 575} // Predicates = [IsRV64] 576 577def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>; 578def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>; 579def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>; 580 581let Predicates = [IsRV64] in { 582def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>; 583def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs, 0)>; 584} // Predicates = [IsRV64] 585 586def : InstAlias<"seqz $rd, $rs", (SLTIU GPR:$rd, GPR:$rs, 1)>; 587def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>; 588def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>; 589def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>; 590 591// sgt/sgtu are recognised by the GNU assembler but the canonical slt/sltu 592// form will always be printed. Therefore, set a zero weight. 593def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>; 594def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>; 595 596def : InstAlias<"beqz $rs, $offset", 597 (BEQ GPR:$rs, X0, simm13_lsb0:$offset)>; 598def : InstAlias<"bnez $rs, $offset", 599 (BNE GPR:$rs, X0, simm13_lsb0:$offset)>; 600def : InstAlias<"blez $rs, $offset", 601 (BGE X0, GPR:$rs, simm13_lsb0:$offset)>; 602def : InstAlias<"bgez $rs, $offset", 603 (BGE GPR:$rs, X0, simm13_lsb0:$offset)>; 604def : InstAlias<"bltz $rs, $offset", 605 (BLT GPR:$rs, X0, simm13_lsb0:$offset)>; 606def : InstAlias<"bgtz $rs, $offset", 607 (BLT X0, GPR:$rs, simm13_lsb0:$offset)>; 608 609// Always output the canonical mnemonic for the pseudo branch instructions. 610// The GNU tools emit the canonical mnemonic for the branch pseudo instructions 611// as well (e.g. "bgt" will be recognised by the assembler but never printed by 612// objdump). Match this behaviour by setting a zero weight. 613def : InstAlias<"bgt $rs, $rt, $offset", 614 (BLT GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; 615def : InstAlias<"ble $rs, $rt, $offset", 616 (BGE GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; 617def : InstAlias<"bgtu $rs, $rt, $offset", 618 (BLTU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; 619def : InstAlias<"bleu $rs, $rt, $offset", 620 (BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; 621 622def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>; 623def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>; 624 625// Non-zero offset aliases of "jalr" are the lowest weight, followed by the 626// two-register form, then the one-register forms and finally "ret". 627def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>; 628def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>; 629def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>; 630def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>; 631def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>; 632def : InstAlias<"ret", (JALR X0, X1, 0), 4>; 633 634// Non-canonical forms for jump targets also accepted by the assembler. 635def : InstAlias<"jr $rs, $offset", (JALR X0, GPR:$rs, simm12:$offset), 0>; 636def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12:$offset), 0>; 637def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>; 638 639// TODO call 640// TODO tail 641 642def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw 643 644def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0)>; 645def : InstAlias<"rdcycle $rd", (CSRRS GPR:$rd, CYCLE.Encoding, X0)>; 646def : InstAlias<"rdtime $rd", (CSRRS GPR:$rd, TIME.Encoding, X0)>; 647 648let Predicates = [IsRV32] in { 649def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, INSTRETH.Encoding, X0)>; 650def : InstAlias<"rdcycleh $rd", (CSRRS GPR:$rd, CYCLEH.Encoding, X0)>; 651def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, TIMEH.Encoding, X0)>; 652} // Predicates = [IsRV32] 653 654def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>; 655def : InstAlias<"csrw $csr, $rs", (CSRRW X0, csr_sysreg:$csr, GPR:$rs)>; 656def : InstAlias<"csrs $csr, $rs", (CSRRS X0, csr_sysreg:$csr, GPR:$rs)>; 657def : InstAlias<"csrc $csr, $rs", (CSRRC X0, csr_sysreg:$csr, GPR:$rs)>; 658 659def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>; 660def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>; 661def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>; 662 663let EmitPriority = 0 in { 664def : InstAlias<"csrw $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>; 665def : InstAlias<"csrs $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>; 666def : InstAlias<"csrc $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>; 667 668def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>; 669def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>; 670def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>; 671} 672 673def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>; 674def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>; 675 676let EmitPriority = 0 in { 677def : InstAlias<"lb $rd, (${rs1})", 678 (LB GPR:$rd, GPR:$rs1, 0)>; 679def : InstAlias<"lh $rd, (${rs1})", 680 (LH GPR:$rd, GPR:$rs1, 0)>; 681def : InstAlias<"lw $rd, (${rs1})", 682 (LW GPR:$rd, GPR:$rs1, 0)>; 683def : InstAlias<"lbu $rd, (${rs1})", 684 (LBU GPR:$rd, GPR:$rs1, 0)>; 685def : InstAlias<"lhu $rd, (${rs1})", 686 (LHU GPR:$rd, GPR:$rs1, 0)>; 687 688def : InstAlias<"sb $rs2, (${rs1})", 689 (SB GPR:$rs2, GPR:$rs1, 0)>; 690def : InstAlias<"sh $rs2, (${rs1})", 691 (SH GPR:$rs2, GPR:$rs1, 0)>; 692def : InstAlias<"sw $rs2, (${rs1})", 693 (SW GPR:$rs2, GPR:$rs1, 0)>; 694 695def : InstAlias<"add $rd, $rs1, $imm12", 696 (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 697def : InstAlias<"and $rd, $rs1, $imm12", 698 (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 699def : InstAlias<"xor $rd, $rs1, $imm12", 700 (XORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 701def : InstAlias<"or $rd, $rs1, $imm12", 702 (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 703def : InstAlias<"sll $rd, $rs1, $shamt", 704 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 705def : InstAlias<"srl $rd, $rs1, $shamt", 706 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 707def : InstAlias<"sra $rd, $rs1, $shamt", 708 (SRAI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 709let Predicates = [IsRV64] in { 710def : InstAlias<"lwu $rd, (${rs1})", 711 (LWU GPR:$rd, GPR:$rs1, 0)>; 712def : InstAlias<"ld $rd, (${rs1})", 713 (LD GPR:$rd, GPR:$rs1, 0)>; 714def : InstAlias<"sd $rs2, (${rs1})", 715 (SD GPR:$rs2, GPR:$rs1, 0)>; 716 717def : InstAlias<"addw $rd, $rs1, $imm12", 718 (ADDIW GPR:$rd, GPR:$rs1, simm12:$imm12)>; 719def : InstAlias<"sllw $rd, $rs1, $shamt", 720 (SLLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; 721def : InstAlias<"srlw $rd, $rs1, $shamt", 722 (SRLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; 723def : InstAlias<"sraw $rd, $rs1, $shamt", 724 (SRAIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>; 725} // Predicates = [IsRV64] 726def : InstAlias<"slt $rd, $rs1, $imm12", 727 (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>; 728def : InstAlias<"sltu $rd, $rs1, $imm12", 729 (SLTIU GPR:$rd, GPR:$rs1, simm12:$imm12)>; 730} 731 732def : MnemonicAlias<"move", "mv">; 733 734// The SCALL and SBREAK instructions wererenamed to ECALL and EBREAK in 735// version 2.1 of the user-level ISA. Like the GNU toolchain, we still accept 736// the old name for backwards compatibility. 737def : MnemonicAlias<"scall", "ecall">; 738def : MnemonicAlias<"sbreak", "ebreak">; 739 740//===----------------------------------------------------------------------===// 741// Pseudo-instructions and codegen patterns 742// 743// Naming convention: For 'generic' pattern classes, we use the naming 744// convention PatTy1Ty2. For pattern classes which offer a more complex 745// expension, prefix the class name, e.g. BccPat. 746//===----------------------------------------------------------------------===// 747 748/// Generic pattern classes 749 750class PatGprGpr<SDPatternOperator OpNode, RVInst Inst> 751 : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>; 752class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst> 753 : Pat<(OpNode GPR:$rs1, simm12:$imm12), (Inst GPR:$rs1, simm12:$imm12)>; 754class PatGprUimmLog2XLen<SDPatternOperator OpNode, RVInstIShift Inst> 755 : Pat<(OpNode GPR:$rs1, uimmlog2xlen:$shamt), 756 (Inst GPR:$rs1, uimmlog2xlen:$shamt)>; 757 758/// Predicates 759 760def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 761 return isOrEquivalentToAdd(N); 762}]>; 763def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{ 764 return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32; 765}]>; 766def sexti32 : PatFrags<(ops node:$src), 767 [(sext_inreg node:$src, i32), 768 (assertsexti32 node:$src)]>; 769def assertzexti32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ 770 return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32; 771}]>; 772def zexti32 : PatFrags<(ops node:$src), 773 [(and node:$src, 0xffffffff), 774 (assertzexti32 node:$src)]>; 775 776/// Immediates 777 778def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>; 779def : Pat<(simm32hi20:$imm), (LUI (HI20 imm:$imm))>; 780def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>, 781 Requires<[IsRV32]>; 782 783/// Simple arithmetic operations 784 785def : PatGprGpr<add, ADD>; 786def : PatGprSimm12<add, ADDI>; 787def : PatGprGpr<sub, SUB>; 788def : PatGprGpr<or, OR>; 789def : PatGprSimm12<or, ORI>; 790def : PatGprGpr<and, AND>; 791def : PatGprSimm12<and, ANDI>; 792def : PatGprGpr<xor, XOR>; 793def : PatGprSimm12<xor, XORI>; 794def : PatGprUimmLog2XLen<shl, SLLI>; 795def : PatGprUimmLog2XLen<srl, SRLI>; 796def : PatGprUimmLog2XLen<sra, SRAI>; 797 798// Match both a plain shift and one where the shift amount is masked (this is 799// typically introduced when the legalizer promotes the shift amount and 800// zero-extends it). For RISC-V, the mask is unnecessary as shifts in the base 801// ISA only read the least significant 5 bits (RV32I) or 6 bits (RV64I). 802class shiftop<SDPatternOperator operator> 803 : PatFrags<(ops node:$val, node:$count), 804 [(operator node:$val, node:$count), 805 (operator node:$val, (and node:$count, immbottomxlenset))]>; 806 807def : PatGprGpr<shiftop<shl>, SLL>; 808def : PatGprGpr<shiftop<srl>, SRL>; 809def : PatGprGpr<shiftop<sra>, SRA>; 810 811// This is a special case of the ADD instruction used to facilitate the use of a 812// fourth operand to emit a relocation on a symbol relating to this instruction. 813// The relocation does not affect any bits of the instruction itself but is used 814// as a hint to the linker. 815let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in 816def PseudoAddTPRel : Pseudo<(outs GPR:$rd), 817 (ins GPR:$rs1, GPR:$rs2, tprel_add_symbol:$src), [], 818 "add", "$rd, $rs1, $rs2, $src">; 819 820/// FrameIndex calculations 821 822def : Pat<(add (i32 AddrFI:$Rs), simm12:$imm12), 823 (ADDI (i32 AddrFI:$Rs), simm12:$imm12)>; 824def : Pat<(IsOrAdd (i32 AddrFI:$Rs), simm12:$imm12), 825 (ADDI (i32 AddrFI:$Rs), simm12:$imm12)>; 826 827/// Setcc 828 829def : PatGprGpr<setlt, SLT>; 830def : PatGprSimm12<setlt, SLTI>; 831def : PatGprGpr<setult, SLTU>; 832def : PatGprSimm12<setult, SLTIU>; 833 834// Define pattern expansions for setcc operations that aren't directly 835// handled by a RISC-V instruction. 836def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>; 837def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>; 838def : Pat<(seteq GPR:$rs1, simm12:$imm12), 839 (SLTIU (XORI GPR:$rs1, simm12:$imm12), 1)>; 840def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>; 841def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>; 842def : Pat<(setne GPR:$rs1, simm12:$imm12), 843 (SLTU X0, (XORI GPR:$rs1, simm12:$imm12))>; 844def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>; 845def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; 846def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>; 847def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>; 848def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>; 849def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>; 850 851let usesCustomInserter = 1 in 852class SelectCC_rrirr<RegisterClass valty, RegisterClass cmpty> 853 : Pseudo<(outs valty:$dst), 854 (ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm, 855 valty:$truev, valty:$falsev), 856 [(set valty:$dst, (riscv_selectcc cmpty:$lhs, cmpty:$rhs, 857 (XLenVT imm:$imm), valty:$truev, valty:$falsev))]>; 858 859def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>; 860 861/// Branches and jumps 862 863// Match `(brcond (CondOp ..), ..)` and lower to the appropriate RISC-V branch 864// instruction. 865class BccPat<PatFrag CondOp, RVInstB Inst> 866 : Pat<(brcond (XLenVT (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12), 867 (Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>; 868 869def : BccPat<seteq, BEQ>; 870def : BccPat<setne, BNE>; 871def : BccPat<setlt, BLT>; 872def : BccPat<setge, BGE>; 873def : BccPat<setult, BLTU>; 874def : BccPat<setuge, BGEU>; 875 876class BccSwapPat<PatFrag CondOp, RVInst InstBcc> 877 : Pat<(brcond (XLenVT (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12), 878 (InstBcc GPR:$rs2, GPR:$rs1, bb:$imm12)>; 879 880// Condition codes that don't have matching RISC-V branch instructions, but 881// are trivially supported by swapping the two input operands 882def : BccSwapPat<setgt, BLT>; 883def : BccSwapPat<setle, BGE>; 884def : BccSwapPat<setugt, BLTU>; 885def : BccSwapPat<setule, BGEU>; 886 887// An extra pattern is needed for a brcond without a setcc (i.e. where the 888// condition was calculated elsewhere). 889def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>; 890 891let isBarrier = 1, isBranch = 1, isTerminator = 1 in 892def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>, 893 PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>; 894 895let isCall = 1, Defs=[X1] in 896let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in 897def PseudoBRIND : Pseudo<(outs), (ins GPR:$rs1, simm12:$imm12), []>, 898 PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>; 899 900def : Pat<(brind GPR:$rs1), (PseudoBRIND GPR:$rs1, 0)>; 901def : Pat<(brind (add GPR:$rs1, simm12:$imm12)), 902 (PseudoBRIND GPR:$rs1, simm12:$imm12)>; 903 904// PsuedoCALLReg is a generic pseudo instruction for calls which will eventually 905// expand to auipc and jalr while encoding, with any given register used as the 906// destination. 907// Define AsmString to print "call" when compile with -S flag. 908// Define isCodeGenOnly = 0 to support parsing assembly "call" instruction. 909let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, hasSideEffects = 0, 910 mayStore = 0, mayLoad = 0 in 911def PseudoCALLReg : Pseudo<(outs GPR:$rd), (ins call_symbol:$func), []> { 912 let AsmString = "call\t$rd, $func"; 913} 914 915// PseudoCALL is a pseudo instruction which will eventually expand to auipc 916// and jalr while encoding. This is desirable, as an auipc+jalr pair with 917// R_RISCV_CALL and R_RISCV_RELAX relocations can be be relaxed by the linker 918// if the offset fits in a signed 21-bit immediate. 919// Define AsmString to print "call" when compile with -S flag. 920// Define isCodeGenOnly = 0 to support parsing assembly "call" instruction. 921let isCall = 1, Defs = [X1], isCodeGenOnly = 0 in 922def PseudoCALL : Pseudo<(outs), (ins call_symbol:$func), []> { 923 let AsmString = "call\t$func"; 924} 925 926def : Pat<(riscv_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>; 927def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>; 928 929def : Pat<(riscv_uret_flag), (URET X0, X0)>; 930def : Pat<(riscv_sret_flag), (SRET X0, X0)>; 931def : Pat<(riscv_mret_flag), (MRET X0, X0)>; 932 933let isCall = 1, Defs = [X1] in 934def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), 935 [(riscv_call GPR:$rs1)]>, 936 PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>; 937 938let isBarrier = 1, isReturn = 1, isTerminator = 1 in 939def PseudoRET : Pseudo<(outs), (ins), [(riscv_ret_flag)]>, 940 PseudoInstExpansion<(JALR X0, X1, 0)>; 941 942// PseudoTAIL is a pseudo instruction similar to PseudoCALL and will eventually 943// expand to auipc and jalr while encoding. 944// Define AsmString to print "tail" when compile with -S flag. 945let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2], 946 isCodeGenOnly = 0 in 947def PseudoTAIL : Pseudo<(outs), (ins call_symbol:$dst), []> { 948 let AsmString = "tail\t$dst"; 949} 950 951let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2] in 952def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1), 953 [(riscv_tail GPRTC:$rs1)]>, 954 PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>; 955 956def : Pat<(riscv_tail (iPTR tglobaladdr:$dst)), 957 (PseudoTAIL texternalsym:$dst)>; 958def : Pat<(riscv_tail (iPTR texternalsym:$dst)), 959 (PseudoTAIL texternalsym:$dst)>; 960 961let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, 962 isAsmParserOnly = 1 in 963def PseudoLLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], 964 "lla", "$dst, $src">; 965 966let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0, 967 isAsmParserOnly = 1 in 968def PseudoLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], 969 "la", "$dst, $src">; 970 971let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0, 972 isAsmParserOnly = 1 in 973def PseudoLA_TLS_IE : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], 974 "la.tls.ie", "$dst, $src">; 975 976let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0, 977 isAsmParserOnly = 1 in 978def PseudoLA_TLS_GD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], 979 "la.tls.gd", "$dst, $src">; 980 981/// Loads 982 983multiclass LdPat<PatFrag LoadOp, RVInst Inst> { 984 def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>; 985 def : Pat<(LoadOp AddrFI:$rs1), (Inst AddrFI:$rs1, 0)>; 986 def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)), 987 (Inst GPR:$rs1, simm12:$imm12)>; 988 def : Pat<(LoadOp (add AddrFI:$rs1, simm12:$imm12)), 989 (Inst AddrFI:$rs1, simm12:$imm12)>; 990 def : Pat<(LoadOp (IsOrAdd AddrFI:$rs1, simm12:$imm12)), 991 (Inst AddrFI:$rs1, simm12:$imm12)>; 992} 993 994defm : LdPat<sextloadi8, LB>; 995defm : LdPat<extloadi8, LB>; 996defm : LdPat<sextloadi16, LH>; 997defm : LdPat<extloadi16, LH>; 998defm : LdPat<load, LW>, Requires<[IsRV32]>; 999defm : LdPat<zextloadi8, LBU>; 1000defm : LdPat<zextloadi16, LHU>; 1001 1002/// Stores 1003 1004multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> { 1005 def : Pat<(StoreOp StTy:$rs2, GPR:$rs1), (Inst StTy:$rs2, GPR:$rs1, 0)>; 1006 def : Pat<(StoreOp StTy:$rs2, AddrFI:$rs1), (Inst StTy:$rs2, AddrFI:$rs1, 0)>; 1007 def : Pat<(StoreOp StTy:$rs2, (add GPR:$rs1, simm12:$imm12)), 1008 (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>; 1009 def : Pat<(StoreOp StTy:$rs2, (add AddrFI:$rs1, simm12:$imm12)), 1010 (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; 1011 def : Pat<(StoreOp StTy:$rs2, (IsOrAdd AddrFI:$rs1, simm12:$imm12)), 1012 (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; 1013} 1014 1015defm : StPat<truncstorei8, SB, GPR>; 1016defm : StPat<truncstorei16, SH, GPR>; 1017defm : StPat<store, SW, GPR>, Requires<[IsRV32]>; 1018 1019/// Fences 1020 1021// Refer to Table A.6 in the version 2.3 draft of the RISC-V Instruction Set 1022// Manual: Volume I. 1023 1024// fence acquire -> fence r, rw 1025def : Pat<(atomic_fence (XLenVT 4), (imm)), (FENCE 0b10, 0b11)>; 1026// fence release -> fence rw, w 1027def : Pat<(atomic_fence (XLenVT 5), (imm)), (FENCE 0b11, 0b1)>; 1028// fence acq_rel -> fence.tso 1029def : Pat<(atomic_fence (XLenVT 6), (imm)), (FENCE_TSO)>; 1030// fence seq_cst -> fence rw, rw 1031def : Pat<(atomic_fence (XLenVT 7), (imm)), (FENCE 0b11, 0b11)>; 1032 1033// Lowering for atomic load and store is defined in RISCVInstrInfoA.td. 1034// Although these are lowered to fence+load/store instructions defined in the 1035// base RV32I/RV64I ISA, this lowering is only used when the A extension is 1036// present. This is necessary as it isn't valid to mix __atomic_* libcalls 1037// with inline atomic operations for the same object. 1038 1039/// Other pseudo-instructions 1040 1041// Pessimistically assume the stack pointer will be clobbered 1042let Defs = [X2], Uses = [X2] in { 1043def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1044 [(callseq_start timm:$amt1, timm:$amt2)]>; 1045def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1046 [(callseq_end timm:$amt1, timm:$amt2)]>; 1047} // Defs = [X2], Uses = [X2] 1048 1049/// RV64 patterns 1050 1051let Predicates = [IsRV64] in { 1052 1053/// sext and zext 1054 1055def : Pat<(sext_inreg GPR:$rs1, i32), (ADDIW GPR:$rs1, 0)>; 1056def : Pat<(and GPR:$rs1, 0xffffffff), (SRLI (SLLI GPR:$rs1, 32), 32)>; 1057 1058/// ALU operations 1059 1060def : Pat<(sext_inreg (add GPR:$rs1, GPR:$rs2), i32), 1061 (ADDW GPR:$rs1, GPR:$rs2)>; 1062def : Pat<(sext_inreg (add GPR:$rs1, simm12:$imm12), i32), 1063 (ADDIW GPR:$rs1, simm12:$imm12)>; 1064def : Pat<(sext_inreg (sub GPR:$rs1, GPR:$rs2), i32), 1065 (SUBW GPR:$rs1, GPR:$rs2)>; 1066def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32), 1067 (SLLIW GPR:$rs1, uimm5:$shamt)>; 1068// (srl (zexti32 ...), uimm5:$shamt) is matched with custom code due to the 1069// need to undo manipulation of the mask value performed by DAGCombine. 1070def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt), 1071 (SRAIW GPR:$rs1, uimm5:$shamt)>; 1072 1073def : PatGprGpr<riscv_sllw, SLLW>; 1074def : PatGprGpr<riscv_srlw, SRLW>; 1075def : PatGprGpr<riscv_sraw, SRAW>; 1076 1077/// Loads 1078 1079defm : LdPat<sextloadi32, LW>; 1080defm : LdPat<extloadi32, LW>; 1081defm : LdPat<zextloadi32, LWU>; 1082defm : LdPat<load, LD>; 1083 1084/// Stores 1085 1086defm : StPat<truncstorei32, SW, GPR>; 1087defm : StPat<store, SD, GPR>; 1088} // Predicates = [IsRV64] 1089 1090/// readcyclecounter 1091// On RV64, we can directly read the 64-bit "cycle" CSR. 1092let Predicates = [IsRV64] in 1093def : Pat<(readcyclecounter), (CSRRS CYCLE.Encoding, X0)>; 1094// On RV32, ReadCycleWide will be expanded to the suggested loop reading both 1095// halves of the 64-bit "cycle" CSR. 1096let Predicates = [IsRV32], usesCustomInserter = 1, hasSideEffects = 0, 1097mayLoad = 0, mayStore = 0, hasNoSchedulingInfo = 1 in 1098def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [], "", "">; 1099 1100//===----------------------------------------------------------------------===// 1101// Standard extensions 1102//===----------------------------------------------------------------------===// 1103 1104include "RISCVInstrInfoM.td" 1105include "RISCVInstrInfoA.td" 1106include "RISCVInstrInfoF.td" 1107include "RISCVInstrInfoD.td" 1108include "RISCVInstrInfoC.td" 1109