1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15 16 #include "RISCVRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "RISCVGenInstrInfo.inc" 21 22 namespace llvm { 23 24 class RISCVSubtarget; 25 26 class RISCVInstrInfo : public RISCVGenInstrInfo { 27 28 public: 29 explicit RISCVInstrInfo(RISCVSubtarget &STI); 30 31 unsigned isLoadFromStackSlot(const MachineInstr &MI, 32 int &FrameIndex) const override; 33 unsigned isStoreToStackSlot(const MachineInstr &MI, 34 int &FrameIndex) const override; 35 36 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 37 const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, 38 bool KillSrc) const override; 39 40 void storeRegToStackSlot(MachineBasicBlock &MBB, 41 MachineBasicBlock::iterator MBBI, unsigned SrcReg, 42 bool IsKill, int FrameIndex, 43 const TargetRegisterClass *RC, 44 const TargetRegisterInfo *TRI) const override; 45 46 void loadRegFromStackSlot(MachineBasicBlock &MBB, 47 MachineBasicBlock::iterator MBBI, unsigned DstReg, 48 int FrameIndex, const TargetRegisterClass *RC, 49 const TargetRegisterInfo *TRI) const override; 50 51 // Materializes the given integer Val into DstReg. 52 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 53 const DebugLoc &DL, Register DstReg, uint64_t Val, 54 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 55 56 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 57 58 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 59 MachineBasicBlock *&FBB, 60 SmallVectorImpl<MachineOperand> &Cond, 61 bool AllowModify) const override; 62 63 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 64 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 65 const DebugLoc &dl, 66 int *BytesAdded = nullptr) const override; 67 68 unsigned insertIndirectBranch(MachineBasicBlock &MBB, 69 MachineBasicBlock &NewDestBB, 70 const DebugLoc &DL, int64_t BrOffset, 71 RegScavenger *RS = nullptr) const override; 72 73 unsigned removeBranch(MachineBasicBlock &MBB, 74 int *BytesRemoved = nullptr) const override; 75 76 bool 77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 78 79 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 80 81 bool isBranchOffsetInRange(unsigned BranchOpc, 82 int64_t BrOffset) const override; 83 84 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 85 86 bool verifyInstruction(const MachineInstr &MI, 87 StringRef &ErrInfo) const override; 88 89 protected: 90 const RISCVSubtarget &STI; 91 }; 92 } 93 #endif 94