1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15 16 #include "RISCVRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 #include "llvm/IR/DiagnosticInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #define GET_INSTRINFO_OPERAND_ENUM 22 #include "RISCVGenInstrInfo.inc" 23 24 namespace llvm { 25 26 class RISCVSubtarget; 27 28 namespace RISCVCC { 29 30 enum CondCode { 31 COND_EQ, 32 COND_NE, 33 COND_LT, 34 COND_GE, 35 COND_LTU, 36 COND_GEU, 37 COND_INVALID 38 }; 39 40 CondCode getOppositeBranchCondition(CondCode); 41 42 } // end of namespace RISCVCC 43 44 class RISCVInstrInfo : public RISCVGenInstrInfo { 45 46 public: 47 explicit RISCVInstrInfo(RISCVSubtarget &STI); 48 49 MCInst getNop() const override; 50 const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const; 51 52 unsigned isLoadFromStackSlot(const MachineInstr &MI, 53 int &FrameIndex) const override; 54 unsigned isStoreToStackSlot(const MachineInstr &MI, 55 int &FrameIndex) const override; 56 57 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 58 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, 59 bool KillSrc) const override; 60 61 void storeRegToStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MBBI, Register SrcReg, 63 bool IsKill, int FrameIndex, 64 const TargetRegisterClass *RC, 65 const TargetRegisterInfo *TRI, 66 Register VReg) const override; 67 68 void loadRegFromStackSlot(MachineBasicBlock &MBB, 69 MachineBasicBlock::iterator MBBI, Register DstReg, 70 int FrameIndex, const TargetRegisterClass *RC, 71 const TargetRegisterInfo *TRI, 72 Register VReg) const override; 73 74 using TargetInstrInfo::foldMemoryOperandImpl; 75 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 76 ArrayRef<unsigned> Ops, 77 MachineBasicBlock::iterator InsertPt, 78 int FrameIndex, 79 LiveIntervals *LIS = nullptr, 80 VirtRegMap *VRM = nullptr) const override; 81 82 // Materializes the given integer Val into DstReg. 83 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 84 const DebugLoc &DL, Register DstReg, uint64_t Val, 85 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 86 87 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 88 89 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 90 MachineBasicBlock *&FBB, 91 SmallVectorImpl<MachineOperand> &Cond, 92 bool AllowModify) const override; 93 94 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 95 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 96 const DebugLoc &dl, 97 int *BytesAdded = nullptr) const override; 98 99 void insertIndirectBranch(MachineBasicBlock &MBB, 100 MachineBasicBlock &NewDestBB, 101 MachineBasicBlock &RestoreBB, const DebugLoc &DL, 102 int64_t BrOffset, RegScavenger *RS) const override; 103 104 unsigned removeBranch(MachineBasicBlock &MBB, 105 int *BytesRemoved = nullptr) const override; 106 107 bool 108 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 109 110 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 111 112 bool isBranchOffsetInRange(unsigned BranchOpc, 113 int64_t BrOffset) const override; 114 115 bool analyzeSelect(const MachineInstr &MI, 116 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 117 unsigned &FalseOp, bool &Optimizable) const override; 118 119 MachineInstr *optimizeSelect(MachineInstr &MI, 120 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 121 bool) const override; 122 123 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 124 125 std::optional<DestSourcePair> 126 isCopyInstrImpl(const MachineInstr &MI) const override; 127 128 bool verifyInstruction(const MachineInstr &MI, 129 StringRef &ErrInfo) const override; 130 131 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 132 const MachineOperand *&BaseOp, 133 int64_t &Offset, unsigned &Width, 134 const TargetRegisterInfo *TRI) const; 135 136 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 137 const MachineInstr &MIb) const override; 138 139 140 std::pair<unsigned, unsigned> 141 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 142 143 ArrayRef<std::pair<unsigned, const char *>> 144 getSerializableDirectMachineOperandTargetFlags() const override; 145 146 // Return true if the function can safely be outlined from. 147 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 148 bool OutlineFromLinkOnceODRs) const override; 149 150 // Return true if MBB is safe to outline from, and return any target-specific 151 // information in Flags. 152 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 153 unsigned &Flags) const override; 154 155 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override; 156 157 // Calculate target-specific information for a set of outlining candidates. 158 outliner::OutlinedFunction getOutliningCandidateInfo( 159 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 160 161 // Return if/how a given MachineInstr should be outlined. 162 outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MBBI, 163 unsigned Flags) const override; 164 165 // Insert a custom frame for outlined functions. 166 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 167 const outliner::OutlinedFunction &OF) const override; 168 169 // Insert a call to an outlined function into a given basic block. 170 MachineBasicBlock::iterator 171 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 172 MachineBasicBlock::iterator &It, MachineFunction &MF, 173 outliner::Candidate &C) const override; 174 175 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 176 unsigned &SrcOpIdx2) const override; 177 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 178 unsigned OpIdx1, 179 unsigned OpIdx2) const override; 180 181 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, 182 LiveIntervals *LIS) const override; 183 184 // MIR printer helper function to annotate Operands with a comment. 185 std::string 186 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 187 unsigned OpIdx, 188 const TargetRegisterInfo *TRI) const override; 189 190 void getVLENFactoredAmount( 191 MachineFunction &MF, MachineBasicBlock &MBB, 192 MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, 193 int64_t Amount, MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 194 195 bool useMachineCombiner() const override { return true; } 196 197 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 198 MachineInstr &NewMI1, 199 MachineInstr &NewMI2) const override; 200 bool 201 getMachineCombinerPatterns(MachineInstr &Root, 202 SmallVectorImpl<MachineCombinerPattern> &Patterns, 203 bool DoRegPressureReduce) const override; 204 205 void 206 finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, 207 SmallVectorImpl<MachineInstr *> &InsInstrs) const override; 208 209 void genAlternativeCodeSequence( 210 MachineInstr &Root, MachineCombinerPattern Pattern, 211 SmallVectorImpl<MachineInstr *> &InsInstrs, 212 SmallVectorImpl<MachineInstr *> &DelInstrs, 213 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 214 215 bool hasReassociableSibling(const MachineInstr &Inst, 216 bool &Commuted) const override; 217 218 bool isAssociativeAndCommutative(const MachineInstr &Inst, 219 bool Invert) const override; 220 221 std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override; 222 223 // Returns true if all uses of OrigMI only depend on the lower \p NBits bits 224 // of its output. 225 bool hasAllNBitUsers(const MachineInstr &MI, const MachineRegisterInfo &MRI, 226 unsigned NBits) const; 227 // Returns true if all uses of OrigMI only depend on the lower word of its 228 // output, so we can transform OrigMI to the corresponding W-version. 229 bool hasAllWUsers(const MachineInstr &MI, 230 const MachineRegisterInfo &MRI) const { 231 return hasAllNBitUsers(MI, MRI, 32); 232 } 233 234 protected: 235 const RISCVSubtarget &STI; 236 }; 237 238 namespace RISCV { 239 240 // Returns true if this is the sext.w pattern, addiw rd, rs1, 0. 241 bool isSEXT_W(const MachineInstr &MI); 242 bool isZEXT_W(const MachineInstr &MI); 243 bool isZEXT_B(const MachineInstr &MI); 244 245 // Returns true if the given MI is an RVV instruction opcode for which we may 246 // expect to see a FrameIndex operand. 247 bool isRVVSpill(const MachineInstr &MI); 248 249 std::optional<std::pair<unsigned, unsigned>> 250 isRVVSpillForZvlsseg(unsigned Opcode); 251 252 bool isFaultFirstLoad(const MachineInstr &MI); 253 254 // Implemented in RISCVGenInstrInfo.inc 255 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 256 257 // Return true if both input instructions have equal rounding mode. If at least 258 // one of the instructions does not have rounding mode, false will be returned. 259 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2); 260 261 // Special immediate for AVL operand of V pseudo instructions to indicate VLMax. 262 static constexpr int64_t VLMaxSentinel = -1LL; 263 264 } // namespace RISCV 265 266 namespace RISCVVPseudosTable { 267 268 struct PseudoInfo { 269 uint16_t Pseudo; 270 uint16_t BaseInstr; 271 }; 272 273 #define GET_RISCVVPseudosTable_DECL 274 #include "RISCVGenSearchableTables.inc" 275 276 } // end namespace RISCVVPseudosTable 277 278 } // end namespace llvm 279 #endif 280