1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15 16 #include "RISCVRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 #include "llvm/IR/DiagnosticInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #define GET_INSTRINFO_OPERAND_ENUM 22 #include "RISCVGenInstrInfo.inc" 23 24 namespace llvm { 25 26 class RISCVSubtarget; 27 28 namespace RISCVCC { 29 30 enum CondCode { 31 COND_EQ, 32 COND_NE, 33 COND_LT, 34 COND_GE, 35 COND_LTU, 36 COND_GEU, 37 COND_INVALID 38 }; 39 40 CondCode getOppositeBranchCondition(CondCode); 41 42 } // end of namespace RISCVCC 43 44 class RISCVInstrInfo : public RISCVGenInstrInfo { 45 46 public: 47 explicit RISCVInstrInfo(RISCVSubtarget &STI); 48 49 MCInst getNop() const override; 50 const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const; 51 52 unsigned isLoadFromStackSlot(const MachineInstr &MI, 53 int &FrameIndex) const override; 54 unsigned isStoreToStackSlot(const MachineInstr &MI, 55 int &FrameIndex) const override; 56 57 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 58 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, 59 bool KillSrc) const override; 60 61 void storeRegToStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MBBI, Register SrcReg, 63 bool IsKill, int FrameIndex, 64 const TargetRegisterClass *RC, 65 const TargetRegisterInfo *TRI) const override; 66 67 void loadRegFromStackSlot(MachineBasicBlock &MBB, 68 MachineBasicBlock::iterator MBBI, Register DstReg, 69 int FrameIndex, const TargetRegisterClass *RC, 70 const TargetRegisterInfo *TRI) const override; 71 72 // Materializes the given integer Val into DstReg. 73 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 74 const DebugLoc &DL, Register DstReg, uint64_t Val, 75 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 76 77 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 78 79 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 80 MachineBasicBlock *&FBB, 81 SmallVectorImpl<MachineOperand> &Cond, 82 bool AllowModify) const override; 83 84 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 85 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 86 const DebugLoc &dl, 87 int *BytesAdded = nullptr) const override; 88 89 void insertIndirectBranch(MachineBasicBlock &MBB, 90 MachineBasicBlock &NewDestBB, 91 MachineBasicBlock &RestoreBB, const DebugLoc &DL, 92 int64_t BrOffset, RegScavenger *RS) const override; 93 94 unsigned removeBranch(MachineBasicBlock &MBB, 95 int *BytesRemoved = nullptr) const override; 96 97 bool 98 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 99 100 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 101 102 bool isBranchOffsetInRange(unsigned BranchOpc, 103 int64_t BrOffset) const override; 104 105 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 106 107 Optional<DestSourcePair> 108 isCopyInstrImpl(const MachineInstr &MI) const override; 109 110 bool verifyInstruction(const MachineInstr &MI, 111 StringRef &ErrInfo) const override; 112 113 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 114 const MachineOperand *&BaseOp, 115 int64_t &Offset, unsigned &Width, 116 const TargetRegisterInfo *TRI) const; 117 118 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 119 const MachineInstr &MIb) const override; 120 121 122 std::pair<unsigned, unsigned> 123 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 124 125 ArrayRef<std::pair<unsigned, const char *>> 126 getSerializableDirectMachineOperandTargetFlags() const override; 127 128 // Return true if the function can safely be outlined from. 129 virtual bool 130 isFunctionSafeToOutlineFrom(MachineFunction &MF, 131 bool OutlineFromLinkOnceODRs) const override; 132 133 // Return true if MBB is safe to outline from, and return any target-specific 134 // information in Flags. 135 virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 136 unsigned &Flags) const override; 137 138 // Calculate target-specific information for a set of outlining candidates. 139 outliner::OutlinedFunction getOutliningCandidateInfo( 140 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 141 142 // Return if/how a given MachineInstr should be outlined. 143 virtual outliner::InstrType 144 getOutliningType(MachineBasicBlock::iterator &MBBI, 145 unsigned Flags) const override; 146 147 // Insert a custom frame for outlined functions. 148 virtual void 149 buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 150 const outliner::OutlinedFunction &OF) const override; 151 152 // Insert a call to an outlined function into a given basic block. 153 virtual MachineBasicBlock::iterator 154 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 155 MachineBasicBlock::iterator &It, MachineFunction &MF, 156 const outliner::Candidate &C) const override; 157 158 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 159 unsigned &SrcOpIdx2) const override; 160 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 161 unsigned OpIdx1, 162 unsigned OpIdx2) const override; 163 164 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, 165 LiveIntervals *LIS) const override; 166 167 Register getVLENFactoredAmount( 168 MachineFunction &MF, MachineBasicBlock &MBB, 169 MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount, 170 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 171 172 // Returns true if the given MI is an RVV instruction opcode for which we may 173 // expect to see a FrameIndex operand. When CheckFIs is true, the instruction 174 // must contain at least one FrameIndex operand. 175 bool isRVVSpill(const MachineInstr &MI, bool CheckFIs) const; 176 177 Optional<std::pair<unsigned, unsigned>> 178 isRVVSpillForZvlsseg(unsigned Opcode) const; 179 180 protected: 181 const RISCVSubtarget &STI; 182 }; 183 184 namespace RISCV { 185 186 // Implemented in RISCVGenInstrInfo.inc 187 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 188 189 // Special immediate for AVL operand of V pseudo instructions to indicate VLMax. 190 static constexpr int64_t VLMaxSentinel = -1LL; 191 } // namespace RISCV 192 193 namespace RISCVVPseudosTable { 194 195 struct PseudoInfo { 196 uint16_t Pseudo; 197 uint16_t BaseInstr; 198 }; 199 200 #define GET_RISCVVPseudosTable_DECL 201 #include "RISCVGenSearchableTables.inc" 202 203 } // end namespace RISCVVPseudosTable 204 205 } // end namespace llvm 206 #endif 207