1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15 16 #include "RISCVRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "RISCVGenInstrInfo.inc" 21 22 namespace llvm { 23 24 class RISCVInstrInfo : public RISCVGenInstrInfo { 25 26 public: 27 RISCVInstrInfo(); 28 29 unsigned isLoadFromStackSlot(const MachineInstr &MI, 30 int &FrameIndex) const override; 31 unsigned isStoreToStackSlot(const MachineInstr &MI, 32 int &FrameIndex) const override; 33 34 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 35 const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, 36 bool KillSrc) const override; 37 38 void storeRegToStackSlot(MachineBasicBlock &MBB, 39 MachineBasicBlock::iterator MBBI, unsigned SrcReg, 40 bool IsKill, int FrameIndex, 41 const TargetRegisterClass *RC, 42 const TargetRegisterInfo *TRI) const override; 43 44 void loadRegFromStackSlot(MachineBasicBlock &MBB, 45 MachineBasicBlock::iterator MBBI, unsigned DstReg, 46 int FrameIndex, const TargetRegisterClass *RC, 47 const TargetRegisterInfo *TRI) const override; 48 49 // Materializes the given int32 Val into DstReg. 50 void movImm32(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 51 const DebugLoc &DL, unsigned DstReg, uint64_t Val, 52 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 53 54 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 55 56 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 57 MachineBasicBlock *&FBB, 58 SmallVectorImpl<MachineOperand> &Cond, 59 bool AllowModify) const override; 60 61 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 62 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 63 const DebugLoc &dl, 64 int *BytesAdded = nullptr) const override; 65 66 unsigned insertIndirectBranch(MachineBasicBlock &MBB, 67 MachineBasicBlock &NewDestBB, 68 const DebugLoc &DL, int64_t BrOffset, 69 RegScavenger *RS = nullptr) const override; 70 71 unsigned removeBranch(MachineBasicBlock &MBB, 72 int *BytesRemoved = nullptr) const override; 73 74 bool 75 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 76 77 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 78 79 bool isBranchOffsetInRange(unsigned BranchOpc, 80 int64_t BrOffset) const override; 81 82 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 83 }; 84 } 85 #endif 86