10b57cec5SDimitry Andric //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the RISCV implementation of the TargetInstrInfo class. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "RISCVRegisterInfo.h" 170b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER 200b57cec5SDimitry Andric #include "RISCVGenInstrInfo.inc" 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric namespace llvm { 230b57cec5SDimitry Andric 24*8bcb0991SDimitry Andric class RISCVSubtarget; 25*8bcb0991SDimitry Andric 260b57cec5SDimitry Andric class RISCVInstrInfo : public RISCVGenInstrInfo { 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric public: 29*8bcb0991SDimitry Andric explicit RISCVInstrInfo(RISCVSubtarget &STI); 300b57cec5SDimitry Andric 310b57cec5SDimitry Andric unsigned isLoadFromStackSlot(const MachineInstr &MI, 320b57cec5SDimitry Andric int &FrameIndex) const override; 330b57cec5SDimitry Andric unsigned isStoreToStackSlot(const MachineInstr &MI, 340b57cec5SDimitry Andric int &FrameIndex) const override; 350b57cec5SDimitry Andric 360b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 370b57cec5SDimitry Andric const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, 380b57cec5SDimitry Andric bool KillSrc) const override; 390b57cec5SDimitry Andric 400b57cec5SDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 410b57cec5SDimitry Andric MachineBasicBlock::iterator MBBI, unsigned SrcReg, 420b57cec5SDimitry Andric bool IsKill, int FrameIndex, 430b57cec5SDimitry Andric const TargetRegisterClass *RC, 440b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const override; 450b57cec5SDimitry Andric 460b57cec5SDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 470b57cec5SDimitry Andric MachineBasicBlock::iterator MBBI, unsigned DstReg, 480b57cec5SDimitry Andric int FrameIndex, const TargetRegisterClass *RC, 490b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const override; 500b57cec5SDimitry Andric 51*8bcb0991SDimitry Andric // Materializes the given integer Val into DstReg. 52*8bcb0991SDimitry Andric void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 53*8bcb0991SDimitry Andric const DebugLoc &DL, Register DstReg, uint64_t Val, 540b57cec5SDimitry Andric MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 550b57cec5SDimitry Andric 560b57cec5SDimitry Andric unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 570b57cec5SDimitry Andric 580b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 590b57cec5SDimitry Andric MachineBasicBlock *&FBB, 600b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 610b57cec5SDimitry Andric bool AllowModify) const override; 620b57cec5SDimitry Andric 630b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 640b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 650b57cec5SDimitry Andric const DebugLoc &dl, 660b57cec5SDimitry Andric int *BytesAdded = nullptr) const override; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric unsigned insertIndirectBranch(MachineBasicBlock &MBB, 690b57cec5SDimitry Andric MachineBasicBlock &NewDestBB, 700b57cec5SDimitry Andric const DebugLoc &DL, int64_t BrOffset, 710b57cec5SDimitry Andric RegScavenger *RS = nullptr) const override; 720b57cec5SDimitry Andric 730b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 740b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override; 750b57cec5SDimitry Andric 760b57cec5SDimitry Andric bool 770b57cec5SDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 780b57cec5SDimitry Andric 790b57cec5SDimitry Andric MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 800b57cec5SDimitry Andric 810b57cec5SDimitry Andric bool isBranchOffsetInRange(unsigned BranchOpc, 820b57cec5SDimitry Andric int64_t BrOffset) const override; 830b57cec5SDimitry Andric 840b57cec5SDimitry Andric bool isAsCheapAsAMove(const MachineInstr &MI) const override; 85*8bcb0991SDimitry Andric 86*8bcb0991SDimitry Andric bool verifyInstruction(const MachineInstr &MI, 87*8bcb0991SDimitry Andric StringRef &ErrInfo) const override; 88*8bcb0991SDimitry Andric 89*8bcb0991SDimitry Andric protected: 90*8bcb0991SDimitry Andric const RISCVSubtarget &STI; 910b57cec5SDimitry Andric }; 920b57cec5SDimitry Andric } 930b57cec5SDimitry Andric #endif 94