1*0b57cec5SDimitry Andric //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file contains the RISCV implementation of the TargetInstrInfo class. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "RISCVRegisterInfo.h" 17*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER 20*0b57cec5SDimitry Andric #include "RISCVGenInstrInfo.inc" 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric namespace llvm { 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andric class RISCVInstrInfo : public RISCVGenInstrInfo { 25*0b57cec5SDimitry Andric 26*0b57cec5SDimitry Andric public: 27*0b57cec5SDimitry Andric RISCVInstrInfo(); 28*0b57cec5SDimitry Andric 29*0b57cec5SDimitry Andric unsigned isLoadFromStackSlot(const MachineInstr &MI, 30*0b57cec5SDimitry Andric int &FrameIndex) const override; 31*0b57cec5SDimitry Andric unsigned isStoreToStackSlot(const MachineInstr &MI, 32*0b57cec5SDimitry Andric int &FrameIndex) const override; 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 35*0b57cec5SDimitry Andric const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, 36*0b57cec5SDimitry Andric bool KillSrc) const override; 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 39*0b57cec5SDimitry Andric MachineBasicBlock::iterator MBBI, unsigned SrcReg, 40*0b57cec5SDimitry Andric bool IsKill, int FrameIndex, 41*0b57cec5SDimitry Andric const TargetRegisterClass *RC, 42*0b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const override; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 45*0b57cec5SDimitry Andric MachineBasicBlock::iterator MBBI, unsigned DstReg, 46*0b57cec5SDimitry Andric int FrameIndex, const TargetRegisterClass *RC, 47*0b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const override; 48*0b57cec5SDimitry Andric 49*0b57cec5SDimitry Andric // Materializes the given int32 Val into DstReg. 50*0b57cec5SDimitry Andric void movImm32(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 51*0b57cec5SDimitry Andric const DebugLoc &DL, unsigned DstReg, uint64_t Val, 52*0b57cec5SDimitry Andric MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 53*0b57cec5SDimitry Andric 54*0b57cec5SDimitry Andric unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 55*0b57cec5SDimitry Andric 56*0b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 57*0b57cec5SDimitry Andric MachineBasicBlock *&FBB, 58*0b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 59*0b57cec5SDimitry Andric bool AllowModify) const override; 60*0b57cec5SDimitry Andric 61*0b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 62*0b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 63*0b57cec5SDimitry Andric const DebugLoc &dl, 64*0b57cec5SDimitry Andric int *BytesAdded = nullptr) const override; 65*0b57cec5SDimitry Andric 66*0b57cec5SDimitry Andric unsigned insertIndirectBranch(MachineBasicBlock &MBB, 67*0b57cec5SDimitry Andric MachineBasicBlock &NewDestBB, 68*0b57cec5SDimitry Andric const DebugLoc &DL, int64_t BrOffset, 69*0b57cec5SDimitry Andric RegScavenger *RS = nullptr) const override; 70*0b57cec5SDimitry Andric 71*0b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 72*0b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override; 73*0b57cec5SDimitry Andric 74*0b57cec5SDimitry Andric bool 75*0b57cec5SDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 76*0b57cec5SDimitry Andric 77*0b57cec5SDimitry Andric MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 78*0b57cec5SDimitry Andric 79*0b57cec5SDimitry Andric bool isBranchOffsetInRange(unsigned BranchOpc, 80*0b57cec5SDimitry Andric int64_t BrOffset) const override; 81*0b57cec5SDimitry Andric 82*0b57cec5SDimitry Andric bool isAsCheapAsAMove(const MachineInstr &MI) const override; 83*0b57cec5SDimitry Andric }; 84*0b57cec5SDimitry Andric } 85*0b57cec5SDimitry Andric #endif 86