1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVInstrInfo.h" 14 #include "MCTargetDesc/RISCVMatInt.h" 15 #include "RISCV.h" 16 #include "RISCVMachineFunctionInfo.h" 17 #include "RISCVSubtarget.h" 18 #include "RISCVTargetMachine.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/Analysis/MemoryLocation.h" 22 #include "llvm/CodeGen/LiveIntervals.h" 23 #include "llvm/CodeGen/LiveVariables.h" 24 #include "llvm/CodeGen/MachineFunctionPass.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/RegisterScavenging.h" 28 #include "llvm/MC/MCInstBuilder.h" 29 #include "llvm/MC/TargetRegistry.h" 30 #include "llvm/Support/ErrorHandling.h" 31 32 using namespace llvm; 33 34 #define GEN_CHECK_COMPRESS_INSTR 35 #include "RISCVGenCompressInstEmitter.inc" 36 37 #define GET_INSTRINFO_CTOR_DTOR 38 #define GET_INSTRINFO_NAMED_OPS 39 #include "RISCVGenInstrInfo.inc" 40 41 static cl::opt<bool> PreferWholeRegisterMove( 42 "riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, 43 cl::desc("Prefer whole register move for vector registers.")); 44 45 namespace llvm { 46 namespace RISCVVPseudosTable { 47 48 using namespace RISCV; 49 50 #define GET_RISCVVPseudosTable_IMPL 51 #include "RISCVGenSearchableTables.inc" 52 53 } // namespace RISCVVPseudosTable 54 } // namespace llvm 55 56 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI) 57 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), 58 STI(STI) {} 59 60 MCInst RISCVInstrInfo::getNop() const { 61 if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) 62 return MCInstBuilder(RISCV::C_NOP); 63 return MCInstBuilder(RISCV::ADDI) 64 .addReg(RISCV::X0) 65 .addReg(RISCV::X0) 66 .addImm(0); 67 } 68 69 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 70 int &FrameIndex) const { 71 switch (MI.getOpcode()) { 72 default: 73 return 0; 74 case RISCV::LB: 75 case RISCV::LBU: 76 case RISCV::LH: 77 case RISCV::LHU: 78 case RISCV::FLH: 79 case RISCV::LW: 80 case RISCV::FLW: 81 case RISCV::LWU: 82 case RISCV::LD: 83 case RISCV::FLD: 84 break; 85 } 86 87 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 88 MI.getOperand(2).getImm() == 0) { 89 FrameIndex = MI.getOperand(1).getIndex(); 90 return MI.getOperand(0).getReg(); 91 } 92 93 return 0; 94 } 95 96 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 97 int &FrameIndex) const { 98 switch (MI.getOpcode()) { 99 default: 100 return 0; 101 case RISCV::SB: 102 case RISCV::SH: 103 case RISCV::SW: 104 case RISCV::FSH: 105 case RISCV::FSW: 106 case RISCV::SD: 107 case RISCV::FSD: 108 break; 109 } 110 111 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 112 MI.getOperand(2).getImm() == 0) { 113 FrameIndex = MI.getOperand(1).getIndex(); 114 return MI.getOperand(0).getReg(); 115 } 116 117 return 0; 118 } 119 120 static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg, 121 unsigned NumRegs) { 122 return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs; 123 } 124 125 static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI, 126 const MachineBasicBlock &MBB, 127 MachineBasicBlock::const_iterator MBBI, 128 MachineBasicBlock::const_iterator &DefMBBI, 129 RISCVII::VLMUL LMul) { 130 if (PreferWholeRegisterMove) 131 return false; 132 133 assert(MBBI->getOpcode() == TargetOpcode::COPY && 134 "Unexpected COPY instruction."); 135 Register SrcReg = MBBI->getOperand(1).getReg(); 136 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); 137 138 bool FoundDef = false; 139 bool FirstVSetVLI = false; 140 unsigned FirstSEW = 0; 141 while (MBBI != MBB.begin()) { 142 --MBBI; 143 if (MBBI->isMetaInstruction()) 144 continue; 145 146 if (MBBI->getOpcode() == RISCV::PseudoVSETVLI || 147 MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 || 148 MBBI->getOpcode() == RISCV::PseudoVSETIVLI) { 149 // There is a vsetvli between COPY and source define instruction. 150 // vy = def_vop ... (producing instruction) 151 // ... 152 // vsetvli 153 // ... 154 // vx = COPY vy 155 if (!FoundDef) { 156 if (!FirstVSetVLI) { 157 FirstVSetVLI = true; 158 unsigned FirstVType = MBBI->getOperand(2).getImm(); 159 RISCVII::VLMUL FirstLMul = RISCVVType::getVLMUL(FirstVType); 160 FirstSEW = RISCVVType::getSEW(FirstVType); 161 // The first encountered vsetvli must have the same lmul as the 162 // register class of COPY. 163 if (FirstLMul != LMul) 164 return false; 165 } 166 // Only permit `vsetvli x0, x0, vtype` between COPY and the source 167 // define instruction. 168 if (MBBI->getOperand(0).getReg() != RISCV::X0) 169 return false; 170 if (MBBI->getOperand(1).isImm()) 171 return false; 172 if (MBBI->getOperand(1).getReg() != RISCV::X0) 173 return false; 174 continue; 175 } 176 177 // MBBI is the first vsetvli before the producing instruction. 178 unsigned VType = MBBI->getOperand(2).getImm(); 179 // If there is a vsetvli between COPY and the producing instruction. 180 if (FirstVSetVLI) { 181 // If SEW is different, return false. 182 if (RISCVVType::getSEW(VType) != FirstSEW) 183 return false; 184 } 185 186 // If the vsetvli is tail undisturbed, keep the whole register move. 187 if (!RISCVVType::isTailAgnostic(VType)) 188 return false; 189 190 // The checking is conservative. We only have register classes for 191 // LMUL = 1/2/4/8. We should be able to convert vmv1r.v to vmv.v.v 192 // for fractional LMUL operations. However, we could not use the vsetvli 193 // lmul for widening operations. The result of widening operation is 194 // 2 x LMUL. 195 return LMul == RISCVVType::getVLMUL(VType); 196 } else if (MBBI->isInlineAsm() || MBBI->isCall()) { 197 return false; 198 } else if (MBBI->getNumDefs()) { 199 // Check all the instructions which will change VL. 200 // For example, vleff has implicit def VL. 201 if (MBBI->modifiesRegister(RISCV::VL)) 202 return false; 203 204 // Only converting whole register copies to vmv.v.v when the defining 205 // value appears in the explicit operands. 206 for (const MachineOperand &MO : MBBI->explicit_operands()) { 207 if (!MO.isReg() || !MO.isDef()) 208 continue; 209 if (!FoundDef && TRI->isSubRegisterEq(MO.getReg(), SrcReg)) { 210 // We only permit the source of COPY has the same LMUL as the defined 211 // operand. 212 // There are cases we need to keep the whole register copy if the LMUL 213 // is different. 214 // For example, 215 // $x0 = PseudoVSETIVLI 4, 73 // vsetivli zero, 4, e16,m2,ta,m 216 // $v28m4 = PseudoVWADD_VV_M2 $v26m2, $v8m2 217 // # The COPY may be created by vlmul_trunc intrinsic. 218 // $v26m2 = COPY renamable $v28m2, implicit killed $v28m4 219 // 220 // After widening, the valid value will be 4 x e32 elements. If we 221 // convert the COPY to vmv.v.v, it will only copy 4 x e16 elements. 222 // FIXME: The COPY of subregister of Zvlsseg register will not be able 223 // to convert to vmv.v.[v|i] under the constraint. 224 if (MO.getReg() != SrcReg) 225 return false; 226 227 // In widening reduction instructions with LMUL_1 input vector case, 228 // only checking the LMUL is insufficient due to reduction result is 229 // always LMUL_1. 230 // For example, 231 // $x11 = PseudoVSETIVLI 1, 64 // vsetivli a1, 1, e8, m1, ta, mu 232 // $v8m1 = PseudoVWREDSUM_VS_M1 $v26, $v27 233 // $v26 = COPY killed renamable $v8 234 // After widening, The valid value will be 1 x e16 elements. If we 235 // convert the COPY to vmv.v.v, it will only copy 1 x e8 elements. 236 uint64_t TSFlags = MBBI->getDesc().TSFlags; 237 if (RISCVII::isRVVWideningReduction(TSFlags)) 238 return false; 239 240 // Found the definition. 241 FoundDef = true; 242 DefMBBI = MBBI; 243 // If the producing instruction does not depend on vsetvli, do not 244 // convert COPY to vmv.v.v. For example, VL1R_V or PseudoVRELOAD. 245 if (!RISCVII::hasSEWOp(TSFlags)) 246 return false; 247 break; 248 } 249 } 250 } 251 } 252 253 return false; 254 } 255 256 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 257 MachineBasicBlock::iterator MBBI, 258 const DebugLoc &DL, MCRegister DstReg, 259 MCRegister SrcReg, bool KillSrc) const { 260 if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { 261 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) 262 .addReg(SrcReg, getKillRegState(KillSrc)) 263 .addImm(0); 264 return; 265 } 266 267 // Handle copy from csr 268 if (RISCV::VCSRRegClass.contains(SrcReg) && 269 RISCV::GPRRegClass.contains(DstReg)) { 270 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); 271 BuildMI(MBB, MBBI, DL, get(RISCV::CSRRS), DstReg) 272 .addImm(RISCVSysReg::lookupSysRegByName(TRI.getName(SrcReg))->Encoding) 273 .addReg(RISCV::X0); 274 return; 275 } 276 277 // FPR->FPR copies and VR->VR copies. 278 unsigned Opc; 279 bool IsScalableVector = true; 280 unsigned NF = 1; 281 RISCVII::VLMUL LMul = RISCVII::LMUL_1; 282 unsigned SubRegIdx = RISCV::sub_vrm1_0; 283 if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) { 284 Opc = RISCV::FSGNJ_H; 285 IsScalableVector = false; 286 } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) { 287 Opc = RISCV::FSGNJ_S; 288 IsScalableVector = false; 289 } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) { 290 Opc = RISCV::FSGNJ_D; 291 IsScalableVector = false; 292 } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { 293 Opc = RISCV::PseudoVMV1R_V; 294 LMul = RISCVII::LMUL_1; 295 } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) { 296 Opc = RISCV::PseudoVMV2R_V; 297 LMul = RISCVII::LMUL_2; 298 } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) { 299 Opc = RISCV::PseudoVMV4R_V; 300 LMul = RISCVII::LMUL_4; 301 } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) { 302 Opc = RISCV::PseudoVMV8R_V; 303 LMul = RISCVII::LMUL_8; 304 } else if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) { 305 Opc = RISCV::PseudoVMV1R_V; 306 SubRegIdx = RISCV::sub_vrm1_0; 307 NF = 2; 308 LMul = RISCVII::LMUL_1; 309 } else if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) { 310 Opc = RISCV::PseudoVMV2R_V; 311 SubRegIdx = RISCV::sub_vrm2_0; 312 NF = 2; 313 LMul = RISCVII::LMUL_2; 314 } else if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) { 315 Opc = RISCV::PseudoVMV4R_V; 316 SubRegIdx = RISCV::sub_vrm4_0; 317 NF = 2; 318 LMul = RISCVII::LMUL_4; 319 } else if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) { 320 Opc = RISCV::PseudoVMV1R_V; 321 SubRegIdx = RISCV::sub_vrm1_0; 322 NF = 3; 323 LMul = RISCVII::LMUL_1; 324 } else if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) { 325 Opc = RISCV::PseudoVMV2R_V; 326 SubRegIdx = RISCV::sub_vrm2_0; 327 NF = 3; 328 LMul = RISCVII::LMUL_2; 329 } else if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) { 330 Opc = RISCV::PseudoVMV1R_V; 331 SubRegIdx = RISCV::sub_vrm1_0; 332 NF = 4; 333 LMul = RISCVII::LMUL_1; 334 } else if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) { 335 Opc = RISCV::PseudoVMV2R_V; 336 SubRegIdx = RISCV::sub_vrm2_0; 337 NF = 4; 338 LMul = RISCVII::LMUL_2; 339 } else if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) { 340 Opc = RISCV::PseudoVMV1R_V; 341 SubRegIdx = RISCV::sub_vrm1_0; 342 NF = 5; 343 LMul = RISCVII::LMUL_1; 344 } else if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) { 345 Opc = RISCV::PseudoVMV1R_V; 346 SubRegIdx = RISCV::sub_vrm1_0; 347 NF = 6; 348 LMul = RISCVII::LMUL_1; 349 } else if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) { 350 Opc = RISCV::PseudoVMV1R_V; 351 SubRegIdx = RISCV::sub_vrm1_0; 352 NF = 7; 353 LMul = RISCVII::LMUL_1; 354 } else if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) { 355 Opc = RISCV::PseudoVMV1R_V; 356 SubRegIdx = RISCV::sub_vrm1_0; 357 NF = 8; 358 LMul = RISCVII::LMUL_1; 359 } else { 360 llvm_unreachable("Impossible reg-to-reg copy"); 361 } 362 363 if (IsScalableVector) { 364 bool UseVMV_V_V = false; 365 MachineBasicBlock::const_iterator DefMBBI; 366 unsigned DefExplicitOpNum; 367 unsigned VIOpc; 368 if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { 369 UseVMV_V_V = true; 370 DefExplicitOpNum = DefMBBI->getNumExplicitOperands(); 371 // We only need to handle LMUL = 1/2/4/8 here because we only define 372 // vector register classes for LMUL = 1/2/4/8. 373 switch (LMul) { 374 default: 375 llvm_unreachable("Impossible LMUL for vector register copy."); 376 case RISCVII::LMUL_1: 377 Opc = RISCV::PseudoVMV_V_V_M1; 378 VIOpc = RISCV::PseudoVMV_V_I_M1; 379 break; 380 case RISCVII::LMUL_2: 381 Opc = RISCV::PseudoVMV_V_V_M2; 382 VIOpc = RISCV::PseudoVMV_V_I_M2; 383 break; 384 case RISCVII::LMUL_4: 385 Opc = RISCV::PseudoVMV_V_V_M4; 386 VIOpc = RISCV::PseudoVMV_V_I_M4; 387 break; 388 case RISCVII::LMUL_8: 389 Opc = RISCV::PseudoVMV_V_V_M8; 390 VIOpc = RISCV::PseudoVMV_V_I_M8; 391 break; 392 } 393 } 394 395 bool UseVMV_V_I = false; 396 if (UseVMV_V_V && (DefMBBI->getOpcode() == VIOpc)) { 397 UseVMV_V_I = true; 398 Opc = VIOpc; 399 } 400 401 if (NF == 1) { 402 auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg); 403 if (UseVMV_V_I) 404 MIB = MIB.add(DefMBBI->getOperand(1)); 405 else 406 MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc)); 407 if (UseVMV_V_V) { 408 // The last two arguments of vector instructions are 409 // AVL, SEW. We also need to append the implicit-use vl and vtype. 410 MIB.add(DefMBBI->getOperand(DefExplicitOpNum - 2)); // AVL 411 MIB.add(DefMBBI->getOperand(DefExplicitOpNum - 1)); // SEW 412 MIB.addReg(RISCV::VL, RegState::Implicit); 413 MIB.addReg(RISCV::VTYPE, RegState::Implicit); 414 } 415 } else { 416 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); 417 418 int I = 0, End = NF, Incr = 1; 419 unsigned SrcEncoding = TRI->getEncodingValue(SrcReg); 420 unsigned DstEncoding = TRI->getEncodingValue(DstReg); 421 unsigned LMulVal; 422 bool Fractional; 423 std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul); 424 assert(!Fractional && "It is impossible be fractional lmul here."); 425 if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) { 426 I = NF - 1; 427 End = -1; 428 Incr = -1; 429 } 430 431 for (; I != End; I += Incr) { 432 auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), 433 TRI->getSubReg(DstReg, SubRegIdx + I)); 434 if (UseVMV_V_I) 435 MIB = MIB.add(DefMBBI->getOperand(1)); 436 else 437 MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I), 438 getKillRegState(KillSrc)); 439 if (UseVMV_V_V) { 440 MIB.add(DefMBBI->getOperand(DefExplicitOpNum - 2)); // AVL 441 MIB.add(DefMBBI->getOperand(DefExplicitOpNum - 1)); // SEW 442 MIB.addReg(RISCV::VL, RegState::Implicit); 443 MIB.addReg(RISCV::VTYPE, RegState::Implicit); 444 } 445 } 446 } 447 } else { 448 BuildMI(MBB, MBBI, DL, get(Opc), DstReg) 449 .addReg(SrcReg, getKillRegState(KillSrc)) 450 .addReg(SrcReg, getKillRegState(KillSrc)); 451 } 452 } 453 454 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 455 MachineBasicBlock::iterator I, 456 Register SrcReg, bool IsKill, int FI, 457 const TargetRegisterClass *RC, 458 const TargetRegisterInfo *TRI) const { 459 DebugLoc DL; 460 if (I != MBB.end()) 461 DL = I->getDebugLoc(); 462 463 MachineFunction *MF = MBB.getParent(); 464 MachineFrameInfo &MFI = MF->getFrameInfo(); 465 466 unsigned Opcode; 467 bool IsScalableVector = true; 468 bool IsZvlsseg = true; 469 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { 470 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? 471 RISCV::SW : RISCV::SD; 472 IsScalableVector = false; 473 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { 474 Opcode = RISCV::FSH; 475 IsScalableVector = false; 476 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { 477 Opcode = RISCV::FSW; 478 IsScalableVector = false; 479 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { 480 Opcode = RISCV::FSD; 481 IsScalableVector = false; 482 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { 483 Opcode = RISCV::PseudoVSPILL_M1; 484 IsZvlsseg = false; 485 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { 486 Opcode = RISCV::PseudoVSPILL_M2; 487 IsZvlsseg = false; 488 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { 489 Opcode = RISCV::PseudoVSPILL_M4; 490 IsZvlsseg = false; 491 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { 492 Opcode = RISCV::PseudoVSPILL_M8; 493 IsZvlsseg = false; 494 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) 495 Opcode = RISCV::PseudoVSPILL2_M1; 496 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) 497 Opcode = RISCV::PseudoVSPILL2_M2; 498 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) 499 Opcode = RISCV::PseudoVSPILL2_M4; 500 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) 501 Opcode = RISCV::PseudoVSPILL3_M1; 502 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) 503 Opcode = RISCV::PseudoVSPILL3_M2; 504 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) 505 Opcode = RISCV::PseudoVSPILL4_M1; 506 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) 507 Opcode = RISCV::PseudoVSPILL4_M2; 508 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) 509 Opcode = RISCV::PseudoVSPILL5_M1; 510 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) 511 Opcode = RISCV::PseudoVSPILL6_M1; 512 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC)) 513 Opcode = RISCV::PseudoVSPILL7_M1; 514 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC)) 515 Opcode = RISCV::PseudoVSPILL8_M1; 516 else 517 llvm_unreachable("Can't store this register to stack slot"); 518 519 if (IsScalableVector) { 520 MachineMemOperand *MMO = MF->getMachineMemOperand( 521 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, 522 MemoryLocation::UnknownSize, MFI.getObjectAlign(FI)); 523 524 MFI.setStackID(FI, TargetStackID::ScalableVector); 525 auto MIB = BuildMI(MBB, I, DL, get(Opcode)) 526 .addReg(SrcReg, getKillRegState(IsKill)) 527 .addFrameIndex(FI) 528 .addMemOperand(MMO); 529 if (IsZvlsseg) { 530 // For spilling/reloading Zvlsseg registers, append the dummy field for 531 // the scaled vector length. The argument will be used when expanding 532 // these pseudo instructions. 533 MIB.addReg(RISCV::X0); 534 } 535 } else { 536 MachineMemOperand *MMO = MF->getMachineMemOperand( 537 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, 538 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 539 540 BuildMI(MBB, I, DL, get(Opcode)) 541 .addReg(SrcReg, getKillRegState(IsKill)) 542 .addFrameIndex(FI) 543 .addImm(0) 544 .addMemOperand(MMO); 545 } 546 } 547 548 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 549 MachineBasicBlock::iterator I, 550 Register DstReg, int FI, 551 const TargetRegisterClass *RC, 552 const TargetRegisterInfo *TRI) const { 553 DebugLoc DL; 554 if (I != MBB.end()) 555 DL = I->getDebugLoc(); 556 557 MachineFunction *MF = MBB.getParent(); 558 MachineFrameInfo &MFI = MF->getFrameInfo(); 559 560 unsigned Opcode; 561 bool IsScalableVector = true; 562 bool IsZvlsseg = true; 563 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { 564 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? 565 RISCV::LW : RISCV::LD; 566 IsScalableVector = false; 567 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { 568 Opcode = RISCV::FLH; 569 IsScalableVector = false; 570 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { 571 Opcode = RISCV::FLW; 572 IsScalableVector = false; 573 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { 574 Opcode = RISCV::FLD; 575 IsScalableVector = false; 576 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { 577 Opcode = RISCV::PseudoVRELOAD_M1; 578 IsZvlsseg = false; 579 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { 580 Opcode = RISCV::PseudoVRELOAD_M2; 581 IsZvlsseg = false; 582 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { 583 Opcode = RISCV::PseudoVRELOAD_M4; 584 IsZvlsseg = false; 585 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { 586 Opcode = RISCV::PseudoVRELOAD_M8; 587 IsZvlsseg = false; 588 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) 589 Opcode = RISCV::PseudoVRELOAD2_M1; 590 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) 591 Opcode = RISCV::PseudoVRELOAD2_M2; 592 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) 593 Opcode = RISCV::PseudoVRELOAD2_M4; 594 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) 595 Opcode = RISCV::PseudoVRELOAD3_M1; 596 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) 597 Opcode = RISCV::PseudoVRELOAD3_M2; 598 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) 599 Opcode = RISCV::PseudoVRELOAD4_M1; 600 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) 601 Opcode = RISCV::PseudoVRELOAD4_M2; 602 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) 603 Opcode = RISCV::PseudoVRELOAD5_M1; 604 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) 605 Opcode = RISCV::PseudoVRELOAD6_M1; 606 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC)) 607 Opcode = RISCV::PseudoVRELOAD7_M1; 608 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC)) 609 Opcode = RISCV::PseudoVRELOAD8_M1; 610 else 611 llvm_unreachable("Can't load this register from stack slot"); 612 613 if (IsScalableVector) { 614 MachineMemOperand *MMO = MF->getMachineMemOperand( 615 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, 616 MemoryLocation::UnknownSize, MFI.getObjectAlign(FI)); 617 618 MFI.setStackID(FI, TargetStackID::ScalableVector); 619 auto MIB = BuildMI(MBB, I, DL, get(Opcode), DstReg) 620 .addFrameIndex(FI) 621 .addMemOperand(MMO); 622 if (IsZvlsseg) { 623 // For spilling/reloading Zvlsseg registers, append the dummy field for 624 // the scaled vector length. The argument will be used when expanding 625 // these pseudo instructions. 626 MIB.addReg(RISCV::X0); 627 } 628 } else { 629 MachineMemOperand *MMO = MF->getMachineMemOperand( 630 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, 631 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 632 633 BuildMI(MBB, I, DL, get(Opcode), DstReg) 634 .addFrameIndex(FI) 635 .addImm(0) 636 .addMemOperand(MMO); 637 } 638 } 639 640 MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl( 641 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 642 MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS, 643 VirtRegMap *VRM) const { 644 const MachineFrameInfo &MFI = MF.getFrameInfo(); 645 646 // The below optimizations narrow the load so they are only valid for little 647 // endian. 648 // TODO: Support big endian by adding an offset into the frame object? 649 if (MF.getDataLayout().isBigEndian()) 650 return nullptr; 651 652 // Fold load from stack followed by sext.w into lw. 653 // TODO: Fold with sext.b, sext.h, zext.b, zext.h, zext.w? 654 if (Ops.size() != 1 || Ops[0] != 1) 655 return nullptr; 656 657 unsigned LoadOpc; 658 switch (MI.getOpcode()) { 659 default: 660 if (RISCV::isSEXT_W(MI)) { 661 LoadOpc = RISCV::LW; 662 break; 663 } 664 if (RISCV::isZEXT_W(MI)) { 665 LoadOpc = RISCV::LWU; 666 break; 667 } 668 if (RISCV::isZEXT_B(MI)) { 669 LoadOpc = RISCV::LBU; 670 break; 671 } 672 return nullptr; 673 case RISCV::SEXT_H: 674 LoadOpc = RISCV::LH; 675 break; 676 case RISCV::SEXT_B: 677 LoadOpc = RISCV::LB; 678 break; 679 case RISCV::ZEXT_H_RV32: 680 case RISCV::ZEXT_H_RV64: 681 LoadOpc = RISCV::LHU; 682 break; 683 } 684 685 MachineMemOperand *MMO = MF.getMachineMemOperand( 686 MachinePointerInfo::getFixedStack(MF, FrameIndex), 687 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex), 688 MFI.getObjectAlign(FrameIndex)); 689 690 Register DstReg = MI.getOperand(0).getReg(); 691 return BuildMI(*MI.getParent(), InsertPt, MI.getDebugLoc(), get(LoadOpc), 692 DstReg) 693 .addFrameIndex(FrameIndex) 694 .addImm(0) 695 .addMemOperand(MMO); 696 } 697 698 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB, 699 MachineBasicBlock::iterator MBBI, 700 const DebugLoc &DL, Register DstReg, uint64_t Val, 701 MachineInstr::MIFlag Flag) const { 702 Register SrcReg = RISCV::X0; 703 704 if (!STI.is64Bit() && !isInt<32>(Val)) 705 report_fatal_error("Should only materialize 32-bit constants for RV32"); 706 707 RISCVMatInt::InstSeq Seq = 708 RISCVMatInt::generateInstSeq(Val, STI.getFeatureBits()); 709 assert(!Seq.empty()); 710 711 for (RISCVMatInt::Inst &Inst : Seq) { 712 switch (Inst.getOpndKind()) { 713 case RISCVMatInt::Imm: 714 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg) 715 .addImm(Inst.Imm) 716 .setMIFlag(Flag); 717 break; 718 case RISCVMatInt::RegX0: 719 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg) 720 .addReg(SrcReg, RegState::Kill) 721 .addReg(RISCV::X0) 722 .setMIFlag(Flag); 723 break; 724 case RISCVMatInt::RegReg: 725 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg) 726 .addReg(SrcReg, RegState::Kill) 727 .addReg(SrcReg, RegState::Kill) 728 .setMIFlag(Flag); 729 break; 730 case RISCVMatInt::RegImm: 731 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg) 732 .addReg(SrcReg, RegState::Kill) 733 .addImm(Inst.Imm) 734 .setMIFlag(Flag); 735 break; 736 } 737 738 // Only the first instruction has X0 as its source. 739 SrcReg = DstReg; 740 } 741 } 742 743 static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) { 744 switch (Opc) { 745 default: 746 return RISCVCC::COND_INVALID; 747 case RISCV::BEQ: 748 return RISCVCC::COND_EQ; 749 case RISCV::BNE: 750 return RISCVCC::COND_NE; 751 case RISCV::BLT: 752 return RISCVCC::COND_LT; 753 case RISCV::BGE: 754 return RISCVCC::COND_GE; 755 case RISCV::BLTU: 756 return RISCVCC::COND_LTU; 757 case RISCV::BGEU: 758 return RISCVCC::COND_GEU; 759 } 760 } 761 762 // The contents of values added to Cond are not examined outside of 763 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we 764 // push BranchOpcode, Reg1, Reg2. 765 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target, 766 SmallVectorImpl<MachineOperand> &Cond) { 767 // Block ends with fall-through condbranch. 768 assert(LastInst.getDesc().isConditionalBranch() && 769 "Unknown conditional branch"); 770 Target = LastInst.getOperand(2).getMBB(); 771 unsigned CC = getCondFromBranchOpc(LastInst.getOpcode()); 772 Cond.push_back(MachineOperand::CreateImm(CC)); 773 Cond.push_back(LastInst.getOperand(0)); 774 Cond.push_back(LastInst.getOperand(1)); 775 } 776 777 const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC) const { 778 switch (CC) { 779 default: 780 llvm_unreachable("Unknown condition code!"); 781 case RISCVCC::COND_EQ: 782 return get(RISCV::BEQ); 783 case RISCVCC::COND_NE: 784 return get(RISCV::BNE); 785 case RISCVCC::COND_LT: 786 return get(RISCV::BLT); 787 case RISCVCC::COND_GE: 788 return get(RISCV::BGE); 789 case RISCVCC::COND_LTU: 790 return get(RISCV::BLTU); 791 case RISCVCC::COND_GEU: 792 return get(RISCV::BGEU); 793 } 794 } 795 796 RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) { 797 switch (CC) { 798 default: 799 llvm_unreachable("Unrecognized conditional branch"); 800 case RISCVCC::COND_EQ: 801 return RISCVCC::COND_NE; 802 case RISCVCC::COND_NE: 803 return RISCVCC::COND_EQ; 804 case RISCVCC::COND_LT: 805 return RISCVCC::COND_GE; 806 case RISCVCC::COND_GE: 807 return RISCVCC::COND_LT; 808 case RISCVCC::COND_LTU: 809 return RISCVCC::COND_GEU; 810 case RISCVCC::COND_GEU: 811 return RISCVCC::COND_LTU; 812 } 813 } 814 815 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB, 816 MachineBasicBlock *&TBB, 817 MachineBasicBlock *&FBB, 818 SmallVectorImpl<MachineOperand> &Cond, 819 bool AllowModify) const { 820 TBB = FBB = nullptr; 821 Cond.clear(); 822 823 // If the block has no terminators, it just falls into the block after it. 824 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 825 if (I == MBB.end() || !isUnpredicatedTerminator(*I)) 826 return false; 827 828 // Count the number of terminators and find the first unconditional or 829 // indirect branch. 830 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end(); 831 int NumTerminators = 0; 832 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J); 833 J++) { 834 NumTerminators++; 835 if (J->getDesc().isUnconditionalBranch() || 836 J->getDesc().isIndirectBranch()) { 837 FirstUncondOrIndirectBr = J.getReverse(); 838 } 839 } 840 841 // If AllowModify is true, we can erase any terminators after 842 // FirstUncondOrIndirectBR. 843 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) { 844 while (std::next(FirstUncondOrIndirectBr) != MBB.end()) { 845 std::next(FirstUncondOrIndirectBr)->eraseFromParent(); 846 NumTerminators--; 847 } 848 I = FirstUncondOrIndirectBr; 849 } 850 851 // We can't handle blocks that end in an indirect branch. 852 if (I->getDesc().isIndirectBranch()) 853 return true; 854 855 // We can't handle blocks with more than 2 terminators. 856 if (NumTerminators > 2) 857 return true; 858 859 // Handle a single unconditional branch. 860 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { 861 TBB = getBranchDestBlock(*I); 862 return false; 863 } 864 865 // Handle a single conditional branch. 866 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { 867 parseCondBranch(*I, TBB, Cond); 868 return false; 869 } 870 871 // Handle a conditional branch followed by an unconditional branch. 872 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && 873 I->getDesc().isUnconditionalBranch()) { 874 parseCondBranch(*std::prev(I), TBB, Cond); 875 FBB = getBranchDestBlock(*I); 876 return false; 877 } 878 879 // Otherwise, we can't handle this. 880 return true; 881 } 882 883 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, 884 int *BytesRemoved) const { 885 if (BytesRemoved) 886 *BytesRemoved = 0; 887 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 888 if (I == MBB.end()) 889 return 0; 890 891 if (!I->getDesc().isUnconditionalBranch() && 892 !I->getDesc().isConditionalBranch()) 893 return 0; 894 895 // Remove the branch. 896 if (BytesRemoved) 897 *BytesRemoved += getInstSizeInBytes(*I); 898 I->eraseFromParent(); 899 900 I = MBB.end(); 901 902 if (I == MBB.begin()) 903 return 1; 904 --I; 905 if (!I->getDesc().isConditionalBranch()) 906 return 1; 907 908 // Remove the branch. 909 if (BytesRemoved) 910 *BytesRemoved += getInstSizeInBytes(*I); 911 I->eraseFromParent(); 912 return 2; 913 } 914 915 // Inserts a branch into the end of the specific MachineBasicBlock, returning 916 // the number of instructions inserted. 917 unsigned RISCVInstrInfo::insertBranch( 918 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, 919 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { 920 if (BytesAdded) 921 *BytesAdded = 0; 922 923 // Shouldn't be a fall through. 924 assert(TBB && "insertBranch must not be told to insert a fallthrough"); 925 assert((Cond.size() == 3 || Cond.size() == 0) && 926 "RISCV branch conditions have two components!"); 927 928 // Unconditional branch. 929 if (Cond.empty()) { 930 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB); 931 if (BytesAdded) 932 *BytesAdded += getInstSizeInBytes(MI); 933 return 1; 934 } 935 936 // Either a one or two-way conditional branch. 937 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); 938 MachineInstr &CondMI = 939 *BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB); 940 if (BytesAdded) 941 *BytesAdded += getInstSizeInBytes(CondMI); 942 943 // One-way conditional branch. 944 if (!FBB) 945 return 1; 946 947 // Two-way conditional branch. 948 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB); 949 if (BytesAdded) 950 *BytesAdded += getInstSizeInBytes(MI); 951 return 2; 952 } 953 954 void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, 955 MachineBasicBlock &DestBB, 956 MachineBasicBlock &RestoreBB, 957 const DebugLoc &DL, int64_t BrOffset, 958 RegScavenger *RS) const { 959 assert(RS && "RegScavenger required for long branching"); 960 assert(MBB.empty() && 961 "new block should be inserted for expanding unconditional branch"); 962 assert(MBB.pred_size() == 1); 963 964 MachineFunction *MF = MBB.getParent(); 965 MachineRegisterInfo &MRI = MF->getRegInfo(); 966 967 if (!isInt<32>(BrOffset)) 968 report_fatal_error( 969 "Branch offsets outside of the signed 32-bit range not supported"); 970 971 // FIXME: A virtual register must be used initially, as the register 972 // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch 973 // uses the same workaround). 974 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 975 auto II = MBB.end(); 976 977 MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump)) 978 .addReg(ScratchReg, RegState::Define | RegState::Dead) 979 .addMBB(&DestBB, RISCVII::MO_CALL); 980 981 RS->enterBasicBlockEnd(MBB); 982 Register Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass, 983 MI.getIterator(), false, 0); 984 // TODO: The case when there is no scavenged register needs special handling. 985 assert(Scav != RISCV::NoRegister && "No register is scavenged!"); 986 MRI.replaceRegWith(ScratchReg, Scav); 987 MRI.clearVirtRegs(); 988 RS->setRegUsed(Scav); 989 } 990 991 bool RISCVInstrInfo::reverseBranchCondition( 992 SmallVectorImpl<MachineOperand> &Cond) const { 993 assert((Cond.size() == 3) && "Invalid branch condition!"); 994 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); 995 Cond[0].setImm(getOppositeBranchCondition(CC)); 996 return false; 997 } 998 999 MachineBasicBlock * 1000 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { 1001 assert(MI.getDesc().isBranch() && "Unexpected opcode!"); 1002 // The branch target is always the last operand. 1003 int NumOp = MI.getNumExplicitOperands(); 1004 return MI.getOperand(NumOp - 1).getMBB(); 1005 } 1006 1007 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp, 1008 int64_t BrOffset) const { 1009 unsigned XLen = STI.getXLen(); 1010 // Ideally we could determine the supported branch offset from the 1011 // RISCVII::FormMask, but this can't be used for Pseudo instructions like 1012 // PseudoBR. 1013 switch (BranchOp) { 1014 default: 1015 llvm_unreachable("Unexpected opcode!"); 1016 case RISCV::BEQ: 1017 case RISCV::BNE: 1018 case RISCV::BLT: 1019 case RISCV::BGE: 1020 case RISCV::BLTU: 1021 case RISCV::BGEU: 1022 return isIntN(13, BrOffset); 1023 case RISCV::JAL: 1024 case RISCV::PseudoBR: 1025 return isIntN(21, BrOffset); 1026 case RISCV::PseudoJump: 1027 return isIntN(32, SignExtend64(BrOffset + 0x800, XLen)); 1028 } 1029 } 1030 1031 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { 1032 if (MI.isMetaInstruction()) 1033 return 0; 1034 1035 unsigned Opcode = MI.getOpcode(); 1036 1037 if (Opcode == TargetOpcode::INLINEASM || 1038 Opcode == TargetOpcode::INLINEASM_BR) { 1039 const MachineFunction &MF = *MI.getParent()->getParent(); 1040 const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget()); 1041 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), 1042 *TM.getMCAsmInfo()); 1043 } 1044 1045 if (MI.getParent() && MI.getParent()->getParent()) { 1046 const auto MF = MI.getMF(); 1047 const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget()); 1048 const MCRegisterInfo &MRI = *TM.getMCRegisterInfo(); 1049 const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo(); 1050 const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>(); 1051 if (isCompressibleInst(MI, &ST, MRI, STI)) 1052 return 2; 1053 } 1054 return get(Opcode).getSize(); 1055 } 1056 1057 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const { 1058 const unsigned Opcode = MI.getOpcode(); 1059 switch (Opcode) { 1060 default: 1061 break; 1062 case RISCV::FSGNJ_D: 1063 case RISCV::FSGNJ_S: 1064 case RISCV::FSGNJ_H: 1065 // The canonical floating-point move is fsgnj rd, rs, rs. 1066 return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && 1067 MI.getOperand(1).getReg() == MI.getOperand(2).getReg(); 1068 case RISCV::ADDI: 1069 case RISCV::ORI: 1070 case RISCV::XORI: 1071 return (MI.getOperand(1).isReg() && 1072 MI.getOperand(1).getReg() == RISCV::X0) || 1073 (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0); 1074 } 1075 return MI.isAsCheapAsAMove(); 1076 } 1077 1078 Optional<DestSourcePair> 1079 RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { 1080 if (MI.isMoveReg()) 1081 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; 1082 switch (MI.getOpcode()) { 1083 default: 1084 break; 1085 case RISCV::ADDI: 1086 // Operand 1 can be a frameindex but callers expect registers 1087 if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() && 1088 MI.getOperand(2).getImm() == 0) 1089 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; 1090 break; 1091 case RISCV::FSGNJ_D: 1092 case RISCV::FSGNJ_S: 1093 case RISCV::FSGNJ_H: 1094 // The canonical floating-point move is fsgnj rd, rs, rs. 1095 if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && 1096 MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) 1097 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; 1098 break; 1099 } 1100 return None; 1101 } 1102 1103 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, 1104 StringRef &ErrInfo) const { 1105 const MCInstrInfo *MCII = STI.getInstrInfo(); 1106 MCInstrDesc const &Desc = MCII->get(MI.getOpcode()); 1107 1108 for (auto &OI : enumerate(Desc.operands())) { 1109 unsigned OpType = OI.value().OperandType; 1110 if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM && 1111 OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) { 1112 const MachineOperand &MO = MI.getOperand(OI.index()); 1113 if (MO.isImm()) { 1114 int64_t Imm = MO.getImm(); 1115 bool Ok; 1116 switch (OpType) { 1117 default: 1118 llvm_unreachable("Unexpected operand type"); 1119 1120 // clang-format off 1121 #define CASE_OPERAND_UIMM(NUM) \ 1122 case RISCVOp::OPERAND_UIMM##NUM: \ 1123 Ok = isUInt<NUM>(Imm); \ 1124 break; 1125 CASE_OPERAND_UIMM(2) 1126 CASE_OPERAND_UIMM(3) 1127 CASE_OPERAND_UIMM(4) 1128 CASE_OPERAND_UIMM(5) 1129 CASE_OPERAND_UIMM(7) 1130 CASE_OPERAND_UIMM(12) 1131 CASE_OPERAND_UIMM(20) 1132 // clang-format on 1133 case RISCVOp::OPERAND_SIMM12: 1134 Ok = isInt<12>(Imm); 1135 break; 1136 case RISCVOp::OPERAND_SIMM12_LSB00000: 1137 Ok = isShiftedInt<7, 5>(Imm); 1138 break; 1139 case RISCVOp::OPERAND_UIMMLOG2XLEN: 1140 if (STI.getTargetTriple().isArch64Bit()) 1141 Ok = isUInt<6>(Imm); 1142 else 1143 Ok = isUInt<5>(Imm); 1144 break; 1145 case RISCVOp::OPERAND_RVKRNUM: 1146 Ok = Imm >= 0 && Imm <= 10; 1147 break; 1148 } 1149 if (!Ok) { 1150 ErrInfo = "Invalid immediate"; 1151 return false; 1152 } 1153 } 1154 } 1155 } 1156 1157 return true; 1158 } 1159 1160 // Return true if get the base operand, byte offset of an instruction and the 1161 // memory width. Width is the size of memory that is being loaded/stored. 1162 bool RISCVInstrInfo::getMemOperandWithOffsetWidth( 1163 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, 1164 unsigned &Width, const TargetRegisterInfo *TRI) const { 1165 if (!LdSt.mayLoadOrStore()) 1166 return false; 1167 1168 // Here we assume the standard RISC-V ISA, which uses a base+offset 1169 // addressing mode. You'll need to relax these conditions to support custom 1170 // load/stores instructions. 1171 if (LdSt.getNumExplicitOperands() != 3) 1172 return false; 1173 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) 1174 return false; 1175 1176 if (!LdSt.hasOneMemOperand()) 1177 return false; 1178 1179 Width = (*LdSt.memoperands_begin())->getSize(); 1180 BaseReg = &LdSt.getOperand(1); 1181 Offset = LdSt.getOperand(2).getImm(); 1182 return true; 1183 } 1184 1185 bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint( 1186 const MachineInstr &MIa, const MachineInstr &MIb) const { 1187 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); 1188 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); 1189 1190 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || 1191 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) 1192 return false; 1193 1194 // Retrieve the base register, offset from the base register and width. Width 1195 // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If 1196 // base registers are identical, and the offset of a lower memory access + 1197 // the width doesn't overlap the offset of a higher memory access, 1198 // then the memory accesses are different. 1199 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); 1200 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; 1201 int64_t OffsetA = 0, OffsetB = 0; 1202 unsigned int WidthA = 0, WidthB = 0; 1203 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && 1204 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { 1205 if (BaseOpA->isIdenticalTo(*BaseOpB)) { 1206 int LowOffset = std::min(OffsetA, OffsetB); 1207 int HighOffset = std::max(OffsetA, OffsetB); 1208 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB; 1209 if (LowOffset + LowWidth <= HighOffset) 1210 return true; 1211 } 1212 } 1213 return false; 1214 } 1215 1216 std::pair<unsigned, unsigned> 1217 RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { 1218 const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK; 1219 return std::make_pair(TF & Mask, TF & ~Mask); 1220 } 1221 1222 ArrayRef<std::pair<unsigned, const char *>> 1223 RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { 1224 using namespace RISCVII; 1225 static const std::pair<unsigned, const char *> TargetFlags[] = { 1226 {MO_CALL, "riscv-call"}, 1227 {MO_PLT, "riscv-plt"}, 1228 {MO_LO, "riscv-lo"}, 1229 {MO_HI, "riscv-hi"}, 1230 {MO_PCREL_LO, "riscv-pcrel-lo"}, 1231 {MO_PCREL_HI, "riscv-pcrel-hi"}, 1232 {MO_GOT_HI, "riscv-got-hi"}, 1233 {MO_TPREL_LO, "riscv-tprel-lo"}, 1234 {MO_TPREL_HI, "riscv-tprel-hi"}, 1235 {MO_TPREL_ADD, "riscv-tprel-add"}, 1236 {MO_TLS_GOT_HI, "riscv-tls-got-hi"}, 1237 {MO_TLS_GD_HI, "riscv-tls-gd-hi"}}; 1238 return makeArrayRef(TargetFlags); 1239 } 1240 bool RISCVInstrInfo::isFunctionSafeToOutlineFrom( 1241 MachineFunction &MF, bool OutlineFromLinkOnceODRs) const { 1242 const Function &F = MF.getFunction(); 1243 1244 // Can F be deduplicated by the linker? If it can, don't outline from it. 1245 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage()) 1246 return false; 1247 1248 // Don't outline from functions with section markings; the program could 1249 // expect that all the code is in the named section. 1250 if (F.hasSection()) 1251 return false; 1252 1253 // It's safe to outline from MF. 1254 return true; 1255 } 1256 1257 bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 1258 unsigned &Flags) const { 1259 // More accurate safety checking is done in getOutliningCandidateInfo. 1260 return TargetInstrInfo::isMBBSafeToOutlineFrom(MBB, Flags); 1261 } 1262 1263 // Enum values indicating how an outlined call should be constructed. 1264 enum MachineOutlinerConstructionID { 1265 MachineOutlinerDefault 1266 }; 1267 1268 bool RISCVInstrInfo::shouldOutlineFromFunctionByDefault( 1269 MachineFunction &MF) const { 1270 return MF.getFunction().hasMinSize(); 1271 } 1272 1273 outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo( 1274 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const { 1275 1276 // First we need to filter out candidates where the X5 register (IE t0) can't 1277 // be used to setup the function call. 1278 auto CannotInsertCall = [](outliner::Candidate &C) { 1279 const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo(); 1280 return !C.isAvailableAcrossAndOutOfSeq(RISCV::X5, *TRI); 1281 }; 1282 1283 llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall); 1284 1285 // If the sequence doesn't have enough candidates left, then we're done. 1286 if (RepeatedSequenceLocs.size() < 2) 1287 return outliner::OutlinedFunction(); 1288 1289 unsigned SequenceSize = 0; 1290 1291 auto I = RepeatedSequenceLocs[0].front(); 1292 auto E = std::next(RepeatedSequenceLocs[0].back()); 1293 for (; I != E; ++I) 1294 SequenceSize += getInstSizeInBytes(*I); 1295 1296 // call t0, function = 8 bytes. 1297 unsigned CallOverhead = 8; 1298 for (auto &C : RepeatedSequenceLocs) 1299 C.setCallInfo(MachineOutlinerDefault, CallOverhead); 1300 1301 // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled. 1302 unsigned FrameOverhead = 4; 1303 if (RepeatedSequenceLocs[0].getMF()->getSubtarget() 1304 .getFeatureBits()[RISCV::FeatureStdExtC]) 1305 FrameOverhead = 2; 1306 1307 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1308 FrameOverhead, MachineOutlinerDefault); 1309 } 1310 1311 outliner::InstrType 1312 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI, 1313 unsigned Flags) const { 1314 MachineInstr &MI = *MBBI; 1315 MachineBasicBlock *MBB = MI.getParent(); 1316 const TargetRegisterInfo *TRI = 1317 MBB->getParent()->getSubtarget().getRegisterInfo(); 1318 1319 // Positions generally can't safely be outlined. 1320 if (MI.isPosition()) { 1321 // We can manually strip out CFI instructions later. 1322 if (MI.isCFIInstruction()) 1323 // If current function has exception handling code, we can't outline & 1324 // strip these CFI instructions since it may break .eh_frame section 1325 // needed in unwinding. 1326 return MI.getMF()->getFunction().needsUnwindTableEntry() 1327 ? outliner::InstrType::Illegal 1328 : outliner::InstrType::Invisible; 1329 1330 return outliner::InstrType::Illegal; 1331 } 1332 1333 // Don't trust the user to write safe inline assembly. 1334 if (MI.isInlineAsm()) 1335 return outliner::InstrType::Illegal; 1336 1337 // We can't outline branches to other basic blocks. 1338 if (MI.isTerminator() && !MBB->succ_empty()) 1339 return outliner::InstrType::Illegal; 1340 1341 // We need support for tail calls to outlined functions before return 1342 // statements can be allowed. 1343 if (MI.isReturn()) 1344 return outliner::InstrType::Illegal; 1345 1346 // Don't allow modifying the X5 register which we use for return addresses for 1347 // these outlined functions. 1348 if (MI.modifiesRegister(RISCV::X5, TRI) || 1349 MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5)) 1350 return outliner::InstrType::Illegal; 1351 1352 // Make sure the operands don't reference something unsafe. 1353 for (const auto &MO : MI.operands()) 1354 if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI() || MO.isJTI()) 1355 return outliner::InstrType::Illegal; 1356 1357 // Don't allow instructions which won't be materialized to impact outlining 1358 // analysis. 1359 if (MI.isMetaInstruction()) 1360 return outliner::InstrType::Invisible; 1361 1362 return outliner::InstrType::Legal; 1363 } 1364 1365 void RISCVInstrInfo::buildOutlinedFrame( 1366 MachineBasicBlock &MBB, MachineFunction &MF, 1367 const outliner::OutlinedFunction &OF) const { 1368 1369 // Strip out any CFI instructions 1370 bool Changed = true; 1371 while (Changed) { 1372 Changed = false; 1373 auto I = MBB.begin(); 1374 auto E = MBB.end(); 1375 for (; I != E; ++I) { 1376 if (I->isCFIInstruction()) { 1377 I->removeFromParent(); 1378 Changed = true; 1379 break; 1380 } 1381 } 1382 } 1383 1384 MBB.addLiveIn(RISCV::X5); 1385 1386 // Add in a return instruction to the end of the outlined frame. 1387 MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR)) 1388 .addReg(RISCV::X0, RegState::Define) 1389 .addReg(RISCV::X5) 1390 .addImm(0)); 1391 } 1392 1393 MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall( 1394 Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, 1395 MachineFunction &MF, outliner::Candidate &C) const { 1396 1397 // Add in a call instruction to the outlined function at the given location. 1398 It = MBB.insert(It, 1399 BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5) 1400 .addGlobalAddress(M.getNamedValue(MF.getName()), 0, 1401 RISCVII::MO_CALL)); 1402 return It; 1403 } 1404 1405 // MIR printer helper function to annotate Operands with a comment. 1406 std::string RISCVInstrInfo::createMIROperandComment( 1407 const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, 1408 const TargetRegisterInfo *TRI) const { 1409 // Print a generic comment for this operand if there is one. 1410 std::string GenericComment = 1411 TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx, TRI); 1412 if (!GenericComment.empty()) 1413 return GenericComment; 1414 1415 // If not, we must have an immediate operand. 1416 if (!Op.isImm()) 1417 return std::string(); 1418 1419 std::string Comment; 1420 raw_string_ostream OS(Comment); 1421 1422 uint64_t TSFlags = MI.getDesc().TSFlags; 1423 1424 // Print the full VType operand of vsetvli/vsetivli instructions, and the SEW 1425 // operand of vector codegen pseudos. 1426 if ((MI.getOpcode() == RISCV::VSETVLI || MI.getOpcode() == RISCV::VSETIVLI || 1427 MI.getOpcode() == RISCV::PseudoVSETVLI || 1428 MI.getOpcode() == RISCV::PseudoVSETIVLI || 1429 MI.getOpcode() == RISCV::PseudoVSETVLIX0) && 1430 OpIdx == 2) { 1431 unsigned Imm = MI.getOperand(OpIdx).getImm(); 1432 RISCVVType::printVType(Imm, OS); 1433 } else if (RISCVII::hasSEWOp(TSFlags)) { 1434 unsigned NumOperands = MI.getNumExplicitOperands(); 1435 bool HasPolicy = RISCVII::hasVecPolicyOp(TSFlags); 1436 1437 // The SEW operand is before any policy operand. 1438 if (OpIdx != NumOperands - HasPolicy - 1) 1439 return std::string(); 1440 1441 unsigned Log2SEW = MI.getOperand(OpIdx).getImm(); 1442 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; 1443 assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); 1444 1445 OS << "e" << SEW; 1446 } 1447 1448 OS.flush(); 1449 return Comment; 1450 } 1451 1452 // clang-format off 1453 #define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL) \ 1454 RISCV::PseudoV##OP##_##TYPE##_##LMUL 1455 1456 #define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE) \ 1457 CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1): \ 1458 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2): \ 1459 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4): \ 1460 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8) 1461 1462 #define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE) \ 1463 CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2): \ 1464 case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE) 1465 1466 #define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE) \ 1467 CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4): \ 1468 case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE) 1469 1470 #define CASE_VFMA_OPCODE_LMULS(OP, TYPE) \ 1471 CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8): \ 1472 case CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE) 1473 1474 #define CASE_VFMA_SPLATS(OP) \ 1475 CASE_VFMA_OPCODE_LMULS_MF4(OP, VF16): \ 1476 case CASE_VFMA_OPCODE_LMULS_MF2(OP, VF32): \ 1477 case CASE_VFMA_OPCODE_LMULS_M1(OP, VF64) 1478 // clang-format on 1479 1480 bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI, 1481 unsigned &SrcOpIdx1, 1482 unsigned &SrcOpIdx2) const { 1483 const MCInstrDesc &Desc = MI.getDesc(); 1484 if (!Desc.isCommutable()) 1485 return false; 1486 1487 switch (MI.getOpcode()) { 1488 case CASE_VFMA_SPLATS(FMADD): 1489 case CASE_VFMA_SPLATS(FMSUB): 1490 case CASE_VFMA_SPLATS(FMACC): 1491 case CASE_VFMA_SPLATS(FMSAC): 1492 case CASE_VFMA_SPLATS(FNMADD): 1493 case CASE_VFMA_SPLATS(FNMSUB): 1494 case CASE_VFMA_SPLATS(FNMACC): 1495 case CASE_VFMA_SPLATS(FNMSAC): 1496 case CASE_VFMA_OPCODE_LMULS_MF4(FMACC, VV): 1497 case CASE_VFMA_OPCODE_LMULS_MF4(FMSAC, VV): 1498 case CASE_VFMA_OPCODE_LMULS_MF4(FNMACC, VV): 1499 case CASE_VFMA_OPCODE_LMULS_MF4(FNMSAC, VV): 1500 case CASE_VFMA_OPCODE_LMULS(MADD, VX): 1501 case CASE_VFMA_OPCODE_LMULS(NMSUB, VX): 1502 case CASE_VFMA_OPCODE_LMULS(MACC, VX): 1503 case CASE_VFMA_OPCODE_LMULS(NMSAC, VX): 1504 case CASE_VFMA_OPCODE_LMULS(MACC, VV): 1505 case CASE_VFMA_OPCODE_LMULS(NMSAC, VV): { 1506 // If the tail policy is undisturbed we can't commute. 1507 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags)); 1508 if ((MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 1) == 0) 1509 return false; 1510 1511 // For these instructions we can only swap operand 1 and operand 3 by 1512 // changing the opcode. 1513 unsigned CommutableOpIdx1 = 1; 1514 unsigned CommutableOpIdx2 = 3; 1515 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1, 1516 CommutableOpIdx2)) 1517 return false; 1518 return true; 1519 } 1520 case CASE_VFMA_OPCODE_LMULS_MF4(FMADD, VV): 1521 case CASE_VFMA_OPCODE_LMULS_MF4(FMSUB, VV): 1522 case CASE_VFMA_OPCODE_LMULS_MF4(FNMADD, VV): 1523 case CASE_VFMA_OPCODE_LMULS_MF4(FNMSUB, VV): 1524 case CASE_VFMA_OPCODE_LMULS(MADD, VV): 1525 case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): { 1526 // If the tail policy is undisturbed we can't commute. 1527 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags)); 1528 if ((MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 1) == 0) 1529 return false; 1530 1531 // For these instructions we have more freedom. We can commute with the 1532 // other multiplicand or with the addend/subtrahend/minuend. 1533 1534 // Any fixed operand must be from source 1, 2 or 3. 1535 if (SrcOpIdx1 != CommuteAnyOperandIndex && SrcOpIdx1 > 3) 1536 return false; 1537 if (SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx2 > 3) 1538 return false; 1539 1540 // It both ops are fixed one must be the tied source. 1541 if (SrcOpIdx1 != CommuteAnyOperandIndex && 1542 SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx1 != 1 && SrcOpIdx2 != 1) 1543 return false; 1544 1545 // Look for two different register operands assumed to be commutable 1546 // regardless of the FMA opcode. The FMA opcode is adjusted later if 1547 // needed. 1548 if (SrcOpIdx1 == CommuteAnyOperandIndex || 1549 SrcOpIdx2 == CommuteAnyOperandIndex) { 1550 // At least one of operands to be commuted is not specified and 1551 // this method is free to choose appropriate commutable operands. 1552 unsigned CommutableOpIdx1 = SrcOpIdx1; 1553 if (SrcOpIdx1 == SrcOpIdx2) { 1554 // Both of operands are not fixed. Set one of commutable 1555 // operands to the tied source. 1556 CommutableOpIdx1 = 1; 1557 } else if (SrcOpIdx1 == CommuteAnyOperandIndex) { 1558 // Only one of the operands is not fixed. 1559 CommutableOpIdx1 = SrcOpIdx2; 1560 } 1561 1562 // CommutableOpIdx1 is well defined now. Let's choose another commutable 1563 // operand and assign its index to CommutableOpIdx2. 1564 unsigned CommutableOpIdx2; 1565 if (CommutableOpIdx1 != 1) { 1566 // If we haven't already used the tied source, we must use it now. 1567 CommutableOpIdx2 = 1; 1568 } else { 1569 Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg(); 1570 1571 // The commuted operands should have different registers. 1572 // Otherwise, the commute transformation does not change anything and 1573 // is useless. We use this as a hint to make our decision. 1574 if (Op1Reg != MI.getOperand(2).getReg()) 1575 CommutableOpIdx2 = 2; 1576 else 1577 CommutableOpIdx2 = 3; 1578 } 1579 1580 // Assign the found pair of commutable indices to SrcOpIdx1 and 1581 // SrcOpIdx2 to return those values. 1582 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1, 1583 CommutableOpIdx2)) 1584 return false; 1585 } 1586 1587 return true; 1588 } 1589 } 1590 1591 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 1592 } 1593 1594 #define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL) \ 1595 case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \ 1596 Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \ 1597 break; 1598 1599 #define CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE) \ 1600 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \ 1601 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \ 1602 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \ 1603 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8) 1604 1605 #define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE) \ 1606 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \ 1607 CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE) 1608 1609 #define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE) \ 1610 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \ 1611 CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE) 1612 1613 #define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \ 1614 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \ 1615 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE) 1616 1617 #define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \ 1618 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VF16) \ 1619 CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VF32) \ 1620 CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VF64) 1621 1622 MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, 1623 bool NewMI, 1624 unsigned OpIdx1, 1625 unsigned OpIdx2) const { 1626 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & { 1627 if (NewMI) 1628 return *MI.getParent()->getParent()->CloneMachineInstr(&MI); 1629 return MI; 1630 }; 1631 1632 switch (MI.getOpcode()) { 1633 case CASE_VFMA_SPLATS(FMACC): 1634 case CASE_VFMA_SPLATS(FMADD): 1635 case CASE_VFMA_SPLATS(FMSAC): 1636 case CASE_VFMA_SPLATS(FMSUB): 1637 case CASE_VFMA_SPLATS(FNMACC): 1638 case CASE_VFMA_SPLATS(FNMADD): 1639 case CASE_VFMA_SPLATS(FNMSAC): 1640 case CASE_VFMA_SPLATS(FNMSUB): 1641 case CASE_VFMA_OPCODE_LMULS_MF4(FMACC, VV): 1642 case CASE_VFMA_OPCODE_LMULS_MF4(FMSAC, VV): 1643 case CASE_VFMA_OPCODE_LMULS_MF4(FNMACC, VV): 1644 case CASE_VFMA_OPCODE_LMULS_MF4(FNMSAC, VV): 1645 case CASE_VFMA_OPCODE_LMULS(MADD, VX): 1646 case CASE_VFMA_OPCODE_LMULS(NMSUB, VX): 1647 case CASE_VFMA_OPCODE_LMULS(MACC, VX): 1648 case CASE_VFMA_OPCODE_LMULS(NMSAC, VX): 1649 case CASE_VFMA_OPCODE_LMULS(MACC, VV): 1650 case CASE_VFMA_OPCODE_LMULS(NMSAC, VV): { 1651 // It only make sense to toggle these between clobbering the 1652 // addend/subtrahend/minuend one of the multiplicands. 1653 assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index"); 1654 assert((OpIdx1 == 3 || OpIdx2 == 3) && "Unexpected opcode index"); 1655 unsigned Opc; 1656 switch (MI.getOpcode()) { 1657 default: 1658 llvm_unreachable("Unexpected opcode"); 1659 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMACC, FMADD) 1660 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMADD, FMACC) 1661 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSAC, FMSUB) 1662 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSUB, FMSAC) 1663 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMACC, FNMADD) 1664 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMADD, FNMACC) 1665 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB) 1666 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC) 1667 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMACC, FMADD, VV) 1668 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMSAC, FMSUB, VV) 1669 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMACC, FNMADD, VV) 1670 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMSAC, FNMSUB, VV) 1671 CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX) 1672 CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX) 1673 CASE_VFMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VX) 1674 CASE_VFMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VX) 1675 CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VV) 1676 CASE_VFMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VV) 1677 } 1678 1679 auto &WorkingMI = cloneIfNew(MI); 1680 WorkingMI.setDesc(get(Opc)); 1681 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 1682 OpIdx1, OpIdx2); 1683 } 1684 case CASE_VFMA_OPCODE_LMULS_MF4(FMADD, VV): 1685 case CASE_VFMA_OPCODE_LMULS_MF4(FMSUB, VV): 1686 case CASE_VFMA_OPCODE_LMULS_MF4(FNMADD, VV): 1687 case CASE_VFMA_OPCODE_LMULS_MF4(FNMSUB, VV): 1688 case CASE_VFMA_OPCODE_LMULS(MADD, VV): 1689 case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): { 1690 assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index"); 1691 // If one of the operands, is the addend we need to change opcode. 1692 // Otherwise we're just swapping 2 of the multiplicands. 1693 if (OpIdx1 == 3 || OpIdx2 == 3) { 1694 unsigned Opc; 1695 switch (MI.getOpcode()) { 1696 default: 1697 llvm_unreachable("Unexpected opcode"); 1698 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMADD, FMACC, VV) 1699 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMSUB, FMSAC, VV) 1700 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMADD, FNMACC, VV) 1701 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMSUB, FNMSAC, VV) 1702 CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VV) 1703 CASE_VFMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VV) 1704 } 1705 1706 auto &WorkingMI = cloneIfNew(MI); 1707 WorkingMI.setDesc(get(Opc)); 1708 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 1709 OpIdx1, OpIdx2); 1710 } 1711 // Let the default code handle it. 1712 break; 1713 } 1714 } 1715 1716 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 1717 } 1718 1719 #undef CASE_VFMA_CHANGE_OPCODE_SPLATS 1720 #undef CASE_VFMA_CHANGE_OPCODE_LMULS 1721 #undef CASE_VFMA_CHANGE_OPCODE_COMMON 1722 #undef CASE_VFMA_SPLATS 1723 #undef CASE_VFMA_OPCODE_LMULS 1724 #undef CASE_VFMA_OPCODE_COMMON 1725 1726 // clang-format off 1727 #define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL) \ 1728 RISCV::PseudoV##OP##_##LMUL##_TIED 1729 1730 #define CASE_WIDEOP_OPCODE_LMULS_MF4(OP) \ 1731 CASE_WIDEOP_OPCODE_COMMON(OP, MF4): \ 1732 case CASE_WIDEOP_OPCODE_COMMON(OP, MF2): \ 1733 case CASE_WIDEOP_OPCODE_COMMON(OP, M1): \ 1734 case CASE_WIDEOP_OPCODE_COMMON(OP, M2): \ 1735 case CASE_WIDEOP_OPCODE_COMMON(OP, M4) 1736 1737 #define CASE_WIDEOP_OPCODE_LMULS(OP) \ 1738 CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \ 1739 case CASE_WIDEOP_OPCODE_LMULS_MF4(OP) 1740 // clang-format on 1741 1742 #define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL) \ 1743 case RISCV::PseudoV##OP##_##LMUL##_TIED: \ 1744 NewOpc = RISCV::PseudoV##OP##_##LMUL; \ 1745 break; 1746 1747 #define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) \ 1748 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \ 1749 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \ 1750 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \ 1751 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \ 1752 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4) 1753 1754 #define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP) \ 1755 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \ 1756 CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) 1757 1758 MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI, 1759 LiveVariables *LV, 1760 LiveIntervals *LIS) const { 1761 switch (MI.getOpcode()) { 1762 default: 1763 break; 1764 case CASE_WIDEOP_OPCODE_LMULS_MF4(FWADD_WV): 1765 case CASE_WIDEOP_OPCODE_LMULS_MF4(FWSUB_WV): 1766 case CASE_WIDEOP_OPCODE_LMULS(WADD_WV): 1767 case CASE_WIDEOP_OPCODE_LMULS(WADDU_WV): 1768 case CASE_WIDEOP_OPCODE_LMULS(WSUB_WV): 1769 case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV): { 1770 // If the tail policy is undisturbed we can't convert. 1771 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) && 1772 MI.getNumExplicitOperands() == 6); 1773 if ((MI.getOperand(5).getImm() & 1) == 0) 1774 return nullptr; 1775 1776 // clang-format off 1777 unsigned NewOpc; 1778 switch (MI.getOpcode()) { 1779 default: 1780 llvm_unreachable("Unexpected opcode"); 1781 CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(FWADD_WV) 1782 CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(FWSUB_WV) 1783 CASE_WIDEOP_CHANGE_OPCODE_LMULS(WADD_WV) 1784 CASE_WIDEOP_CHANGE_OPCODE_LMULS(WADDU_WV) 1785 CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV) 1786 CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUBU_WV) 1787 } 1788 // clang-format on 1789 1790 MachineBasicBlock &MBB = *MI.getParent(); 1791 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc)) 1792 .add(MI.getOperand(0)) 1793 .add(MI.getOperand(1)) 1794 .add(MI.getOperand(2)) 1795 .add(MI.getOperand(3)) 1796 .add(MI.getOperand(4)); 1797 MIB.copyImplicitOps(MI); 1798 1799 if (LV) { 1800 unsigned NumOps = MI.getNumOperands(); 1801 for (unsigned I = 1; I < NumOps; ++I) { 1802 MachineOperand &Op = MI.getOperand(I); 1803 if (Op.isReg() && Op.isKill()) 1804 LV->replaceKillInstruction(Op.getReg(), MI, *MIB); 1805 } 1806 } 1807 1808 if (LIS) { 1809 SlotIndex Idx = LIS->ReplaceMachineInstrInMaps(MI, *MIB); 1810 1811 if (MI.getOperand(0).isEarlyClobber()) { 1812 // Use operand 1 was tied to early-clobber def operand 0, so its live 1813 // interval could have ended at an early-clobber slot. Now they are not 1814 // tied we need to update it to the normal register slot. 1815 LiveInterval &LI = LIS->getInterval(MI.getOperand(1).getReg()); 1816 LiveRange::Segment *S = LI.getSegmentContaining(Idx); 1817 if (S->end == Idx.getRegSlot(true)) 1818 S->end = Idx.getRegSlot(); 1819 } 1820 } 1821 1822 return MIB; 1823 } 1824 } 1825 1826 return nullptr; 1827 } 1828 1829 #undef CASE_WIDEOP_CHANGE_OPCODE_LMULS 1830 #undef CASE_WIDEOP_CHANGE_OPCODE_COMMON 1831 #undef CASE_WIDEOP_OPCODE_LMULS 1832 #undef CASE_WIDEOP_OPCODE_COMMON 1833 1834 Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF, 1835 MachineBasicBlock &MBB, 1836 MachineBasicBlock::iterator II, 1837 const DebugLoc &DL, 1838 int64_t Amount, 1839 MachineInstr::MIFlag Flag) const { 1840 assert(Amount > 0 && "There is no need to get VLEN scaled value."); 1841 assert(Amount % 8 == 0 && 1842 "Reserve the stack by the multiple of one vector size."); 1843 1844 MachineRegisterInfo &MRI = MF.getRegInfo(); 1845 int64_t NumOfVReg = Amount / 8; 1846 1847 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); 1848 BuildMI(MBB, II, DL, get(RISCV::PseudoReadVLENB), VL) 1849 .setMIFlag(Flag); 1850 assert(isInt<32>(NumOfVReg) && 1851 "Expect the number of vector registers within 32-bits."); 1852 if (isPowerOf2_32(NumOfVReg)) { 1853 uint32_t ShiftAmount = Log2_32(NumOfVReg); 1854 if (ShiftAmount == 0) 1855 return VL; 1856 BuildMI(MBB, II, DL, get(RISCV::SLLI), VL) 1857 .addReg(VL, RegState::Kill) 1858 .addImm(ShiftAmount) 1859 .setMIFlag(Flag); 1860 } else if (STI.hasStdExtZba() && 1861 ((NumOfVReg % 3 == 0 && isPowerOf2_64(NumOfVReg / 3)) || 1862 (NumOfVReg % 5 == 0 && isPowerOf2_64(NumOfVReg / 5)) || 1863 (NumOfVReg % 9 == 0 && isPowerOf2_64(NumOfVReg / 9)))) { 1864 // We can use Zba SHXADD+SLLI instructions for multiply in some cases. 1865 unsigned Opc; 1866 uint32_t ShiftAmount; 1867 if (NumOfVReg % 9 == 0) { 1868 Opc = RISCV::SH3ADD; 1869 ShiftAmount = Log2_64(NumOfVReg / 9); 1870 } else if (NumOfVReg % 5 == 0) { 1871 Opc = RISCV::SH2ADD; 1872 ShiftAmount = Log2_64(NumOfVReg / 5); 1873 } else if (NumOfVReg % 3 == 0) { 1874 Opc = RISCV::SH1ADD; 1875 ShiftAmount = Log2_64(NumOfVReg / 3); 1876 } else { 1877 llvm_unreachable("Unexpected number of vregs"); 1878 } 1879 if (ShiftAmount) 1880 BuildMI(MBB, II, DL, get(RISCV::SLLI), VL) 1881 .addReg(VL, RegState::Kill) 1882 .addImm(ShiftAmount) 1883 .setMIFlag(Flag); 1884 BuildMI(MBB, II, DL, get(Opc), VL) 1885 .addReg(VL, RegState::Kill) 1886 .addReg(VL) 1887 .setMIFlag(Flag); 1888 } else if (isPowerOf2_32(NumOfVReg - 1)) { 1889 Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass); 1890 uint32_t ShiftAmount = Log2_32(NumOfVReg - 1); 1891 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) 1892 .addReg(VL) 1893 .addImm(ShiftAmount) 1894 .setMIFlag(Flag); 1895 BuildMI(MBB, II, DL, get(RISCV::ADD), VL) 1896 .addReg(ScaledRegister, RegState::Kill) 1897 .addReg(VL, RegState::Kill) 1898 .setMIFlag(Flag); 1899 } else if (isPowerOf2_32(NumOfVReg + 1)) { 1900 Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass); 1901 uint32_t ShiftAmount = Log2_32(NumOfVReg + 1); 1902 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) 1903 .addReg(VL) 1904 .addImm(ShiftAmount) 1905 .setMIFlag(Flag); 1906 BuildMI(MBB, II, DL, get(RISCV::SUB), VL) 1907 .addReg(ScaledRegister, RegState::Kill) 1908 .addReg(VL, RegState::Kill) 1909 .setMIFlag(Flag); 1910 } else { 1911 Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass); 1912 movImm(MBB, II, DL, N, NumOfVReg, Flag); 1913 if (!STI.hasStdExtM() && !STI.hasStdExtZmmul()) 1914 MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{ 1915 MF.getFunction(), 1916 "M- or Zmmul-extension must be enabled to calculate the vscaled size/" 1917 "offset."}); 1918 BuildMI(MBB, II, DL, get(RISCV::MUL), VL) 1919 .addReg(VL, RegState::Kill) 1920 .addReg(N, RegState::Kill) 1921 .setMIFlag(Flag); 1922 } 1923 1924 return VL; 1925 } 1926 1927 // Returns true if this is the sext.w pattern, addiw rd, rs1, 0. 1928 bool RISCV::isSEXT_W(const MachineInstr &MI) { 1929 return MI.getOpcode() == RISCV::ADDIW && MI.getOperand(1).isReg() && 1930 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0; 1931 } 1932 1933 // Returns true if this is the zext.w pattern, adduw rd, rs1, x0. 1934 bool RISCV::isZEXT_W(const MachineInstr &MI) { 1935 return MI.getOpcode() == RISCV::ADD_UW && MI.getOperand(1).isReg() && 1936 MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0; 1937 } 1938 1939 // Returns true if this is the zext.b pattern, andi rd, rs1, 255. 1940 bool RISCV::isZEXT_B(const MachineInstr &MI) { 1941 return MI.getOpcode() == RISCV::ANDI && MI.getOperand(1).isReg() && 1942 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 255; 1943 } 1944 1945 static bool isRVVWholeLoadStore(unsigned Opcode) { 1946 switch (Opcode) { 1947 default: 1948 return false; 1949 case RISCV::VS1R_V: 1950 case RISCV::VS2R_V: 1951 case RISCV::VS4R_V: 1952 case RISCV::VS8R_V: 1953 case RISCV::VL1RE8_V: 1954 case RISCV::VL2RE8_V: 1955 case RISCV::VL4RE8_V: 1956 case RISCV::VL8RE8_V: 1957 case RISCV::VL1RE16_V: 1958 case RISCV::VL2RE16_V: 1959 case RISCV::VL4RE16_V: 1960 case RISCV::VL8RE16_V: 1961 case RISCV::VL1RE32_V: 1962 case RISCV::VL2RE32_V: 1963 case RISCV::VL4RE32_V: 1964 case RISCV::VL8RE32_V: 1965 case RISCV::VL1RE64_V: 1966 case RISCV::VL2RE64_V: 1967 case RISCV::VL4RE64_V: 1968 case RISCV::VL8RE64_V: 1969 return true; 1970 } 1971 } 1972 1973 bool RISCV::isRVVSpill(const MachineInstr &MI) { 1974 // RVV lacks any support for immediate addressing for stack addresses, so be 1975 // conservative. 1976 unsigned Opcode = MI.getOpcode(); 1977 if (!RISCVVPseudosTable::getPseudoInfo(Opcode) && 1978 !isRVVWholeLoadStore(Opcode) && !isRVVSpillForZvlsseg(Opcode)) 1979 return false; 1980 return true; 1981 } 1982 1983 Optional<std::pair<unsigned, unsigned>> 1984 RISCV::isRVVSpillForZvlsseg(unsigned Opcode) { 1985 switch (Opcode) { 1986 default: 1987 return None; 1988 case RISCV::PseudoVSPILL2_M1: 1989 case RISCV::PseudoVRELOAD2_M1: 1990 return std::make_pair(2u, 1u); 1991 case RISCV::PseudoVSPILL2_M2: 1992 case RISCV::PseudoVRELOAD2_M2: 1993 return std::make_pair(2u, 2u); 1994 case RISCV::PseudoVSPILL2_M4: 1995 case RISCV::PseudoVRELOAD2_M4: 1996 return std::make_pair(2u, 4u); 1997 case RISCV::PseudoVSPILL3_M1: 1998 case RISCV::PseudoVRELOAD3_M1: 1999 return std::make_pair(3u, 1u); 2000 case RISCV::PseudoVSPILL3_M2: 2001 case RISCV::PseudoVRELOAD3_M2: 2002 return std::make_pair(3u, 2u); 2003 case RISCV::PseudoVSPILL4_M1: 2004 case RISCV::PseudoVRELOAD4_M1: 2005 return std::make_pair(4u, 1u); 2006 case RISCV::PseudoVSPILL4_M2: 2007 case RISCV::PseudoVRELOAD4_M2: 2008 return std::make_pair(4u, 2u); 2009 case RISCV::PseudoVSPILL5_M1: 2010 case RISCV::PseudoVRELOAD5_M1: 2011 return std::make_pair(5u, 1u); 2012 case RISCV::PseudoVSPILL6_M1: 2013 case RISCV::PseudoVRELOAD6_M1: 2014 return std::make_pair(6u, 1u); 2015 case RISCV::PseudoVSPILL7_M1: 2016 case RISCV::PseudoVRELOAD7_M1: 2017 return std::make_pair(7u, 1u); 2018 case RISCV::PseudoVSPILL8_M1: 2019 case RISCV::PseudoVRELOAD8_M1: 2020 return std::make_pair(8u, 1u); 2021 } 2022 } 2023 2024 bool RISCV::isFaultFirstLoad(const MachineInstr &MI) { 2025 return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) && 2026 !MI.isInlineAsm(); 2027 } 2028