1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVInstrInfo.h" 14 #include "RISCV.h" 15 #include "RISCVSubtarget.h" 16 #include "RISCVTargetMachine.h" 17 #include "Utils/RISCVMatInt.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/RegisterScavenging.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 27 using namespace llvm; 28 29 #define GEN_CHECK_COMPRESS_INSTR 30 #include "RISCVGenCompressInstEmitter.inc" 31 32 #define GET_INSTRINFO_CTOR_DTOR 33 #include "RISCVGenInstrInfo.inc" 34 35 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI) 36 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), 37 STI(STI) {} 38 39 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 40 int &FrameIndex) const { 41 switch (MI.getOpcode()) { 42 default: 43 return 0; 44 case RISCV::LB: 45 case RISCV::LBU: 46 case RISCV::LH: 47 case RISCV::LHU: 48 case RISCV::LW: 49 case RISCV::FLW: 50 case RISCV::LWU: 51 case RISCV::LD: 52 case RISCV::FLD: 53 break; 54 } 55 56 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 57 MI.getOperand(2).getImm() == 0) { 58 FrameIndex = MI.getOperand(1).getIndex(); 59 return MI.getOperand(0).getReg(); 60 } 61 62 return 0; 63 } 64 65 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 66 int &FrameIndex) const { 67 switch (MI.getOpcode()) { 68 default: 69 return 0; 70 case RISCV::SB: 71 case RISCV::SH: 72 case RISCV::SW: 73 case RISCV::FSW: 74 case RISCV::SD: 75 case RISCV::FSD: 76 break; 77 } 78 79 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 80 MI.getOperand(2).getImm() == 0) { 81 FrameIndex = MI.getOperand(1).getIndex(); 82 return MI.getOperand(0).getReg(); 83 } 84 85 return 0; 86 } 87 88 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 89 MachineBasicBlock::iterator MBBI, 90 const DebugLoc &DL, MCRegister DstReg, 91 MCRegister SrcReg, bool KillSrc) const { 92 if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { 93 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) 94 .addReg(SrcReg, getKillRegState(KillSrc)) 95 .addImm(0); 96 return; 97 } 98 99 // FPR->FPR copies 100 unsigned Opc; 101 if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) 102 Opc = RISCV::FSGNJ_S; 103 else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) 104 Opc = RISCV::FSGNJ_D; 105 else 106 llvm_unreachable("Impossible reg-to-reg copy"); 107 108 BuildMI(MBB, MBBI, DL, get(Opc), DstReg) 109 .addReg(SrcReg, getKillRegState(KillSrc)) 110 .addReg(SrcReg, getKillRegState(KillSrc)); 111 } 112 113 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 114 MachineBasicBlock::iterator I, 115 Register SrcReg, bool IsKill, int FI, 116 const TargetRegisterClass *RC, 117 const TargetRegisterInfo *TRI) const { 118 DebugLoc DL; 119 if (I != MBB.end()) 120 DL = I->getDebugLoc(); 121 122 unsigned Opcode; 123 124 if (RISCV::GPRRegClass.hasSubClassEq(RC)) 125 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? 126 RISCV::SW : RISCV::SD; 127 else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) 128 Opcode = RISCV::FSW; 129 else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) 130 Opcode = RISCV::FSD; 131 else 132 llvm_unreachable("Can't store this register to stack slot"); 133 134 BuildMI(MBB, I, DL, get(Opcode)) 135 .addReg(SrcReg, getKillRegState(IsKill)) 136 .addFrameIndex(FI) 137 .addImm(0); 138 } 139 140 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 141 MachineBasicBlock::iterator I, 142 Register DstReg, int FI, 143 const TargetRegisterClass *RC, 144 const TargetRegisterInfo *TRI) const { 145 DebugLoc DL; 146 if (I != MBB.end()) 147 DL = I->getDebugLoc(); 148 149 unsigned Opcode; 150 151 if (RISCV::GPRRegClass.hasSubClassEq(RC)) 152 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? 153 RISCV::LW : RISCV::LD; 154 else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) 155 Opcode = RISCV::FLW; 156 else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) 157 Opcode = RISCV::FLD; 158 else 159 llvm_unreachable("Can't load this register from stack slot"); 160 161 BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0); 162 } 163 164 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB, 165 MachineBasicBlock::iterator MBBI, 166 const DebugLoc &DL, Register DstReg, uint64_t Val, 167 MachineInstr::MIFlag Flag) const { 168 MachineFunction *MF = MBB.getParent(); 169 MachineRegisterInfo &MRI = MF->getRegInfo(); 170 bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit(); 171 Register SrcReg = RISCV::X0; 172 Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass); 173 unsigned Num = 0; 174 175 if (!IsRV64 && !isInt<32>(Val)) 176 report_fatal_error("Should only materialize 32-bit constants for RV32"); 177 178 RISCVMatInt::InstSeq Seq; 179 RISCVMatInt::generateInstSeq(Val, IsRV64, Seq); 180 assert(Seq.size() > 0); 181 182 for (RISCVMatInt::Inst &Inst : Seq) { 183 // Write the final result to DstReg if it's the last instruction in the Seq. 184 // Otherwise, write the result to the temp register. 185 if (++Num == Seq.size()) 186 Result = DstReg; 187 188 if (Inst.Opc == RISCV::LUI) { 189 BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result) 190 .addImm(Inst.Imm) 191 .setMIFlag(Flag); 192 } else { 193 BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result) 194 .addReg(SrcReg, RegState::Kill) 195 .addImm(Inst.Imm) 196 .setMIFlag(Flag); 197 } 198 // Only the first instruction has X0 as its source. 199 SrcReg = Result; 200 } 201 } 202 203 // The contents of values added to Cond are not examined outside of 204 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we 205 // push BranchOpcode, Reg1, Reg2. 206 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target, 207 SmallVectorImpl<MachineOperand> &Cond) { 208 // Block ends with fall-through condbranch. 209 assert(LastInst.getDesc().isConditionalBranch() && 210 "Unknown conditional branch"); 211 Target = LastInst.getOperand(2).getMBB(); 212 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); 213 Cond.push_back(LastInst.getOperand(0)); 214 Cond.push_back(LastInst.getOperand(1)); 215 } 216 217 static unsigned getOppositeBranchOpcode(int Opc) { 218 switch (Opc) { 219 default: 220 llvm_unreachable("Unrecognized conditional branch"); 221 case RISCV::BEQ: 222 return RISCV::BNE; 223 case RISCV::BNE: 224 return RISCV::BEQ; 225 case RISCV::BLT: 226 return RISCV::BGE; 227 case RISCV::BGE: 228 return RISCV::BLT; 229 case RISCV::BLTU: 230 return RISCV::BGEU; 231 case RISCV::BGEU: 232 return RISCV::BLTU; 233 } 234 } 235 236 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB, 237 MachineBasicBlock *&TBB, 238 MachineBasicBlock *&FBB, 239 SmallVectorImpl<MachineOperand> &Cond, 240 bool AllowModify) const { 241 TBB = FBB = nullptr; 242 Cond.clear(); 243 244 // If the block has no terminators, it just falls into the block after it. 245 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 246 if (I == MBB.end() || !isUnpredicatedTerminator(*I)) 247 return false; 248 249 // Count the number of terminators and find the first unconditional or 250 // indirect branch. 251 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end(); 252 int NumTerminators = 0; 253 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J); 254 J++) { 255 NumTerminators++; 256 if (J->getDesc().isUnconditionalBranch() || 257 J->getDesc().isIndirectBranch()) { 258 FirstUncondOrIndirectBr = J.getReverse(); 259 } 260 } 261 262 // If AllowModify is true, we can erase any terminators after 263 // FirstUncondOrIndirectBR. 264 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) { 265 while (std::next(FirstUncondOrIndirectBr) != MBB.end()) { 266 std::next(FirstUncondOrIndirectBr)->eraseFromParent(); 267 NumTerminators--; 268 } 269 I = FirstUncondOrIndirectBr; 270 } 271 272 // We can't handle blocks that end in an indirect branch. 273 if (I->getDesc().isIndirectBranch()) 274 return true; 275 276 // We can't handle blocks with more than 2 terminators. 277 if (NumTerminators > 2) 278 return true; 279 280 // Handle a single unconditional branch. 281 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { 282 TBB = getBranchDestBlock(*I); 283 return false; 284 } 285 286 // Handle a single conditional branch. 287 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { 288 parseCondBranch(*I, TBB, Cond); 289 return false; 290 } 291 292 // Handle a conditional branch followed by an unconditional branch. 293 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && 294 I->getDesc().isUnconditionalBranch()) { 295 parseCondBranch(*std::prev(I), TBB, Cond); 296 FBB = getBranchDestBlock(*I); 297 return false; 298 } 299 300 // Otherwise, we can't handle this. 301 return true; 302 } 303 304 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, 305 int *BytesRemoved) const { 306 if (BytesRemoved) 307 *BytesRemoved = 0; 308 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 309 if (I == MBB.end()) 310 return 0; 311 312 if (!I->getDesc().isUnconditionalBranch() && 313 !I->getDesc().isConditionalBranch()) 314 return 0; 315 316 // Remove the branch. 317 if (BytesRemoved) 318 *BytesRemoved += getInstSizeInBytes(*I); 319 I->eraseFromParent(); 320 321 I = MBB.end(); 322 323 if (I == MBB.begin()) 324 return 1; 325 --I; 326 if (!I->getDesc().isConditionalBranch()) 327 return 1; 328 329 // Remove the branch. 330 if (BytesRemoved) 331 *BytesRemoved += getInstSizeInBytes(*I); 332 I->eraseFromParent(); 333 return 2; 334 } 335 336 // Inserts a branch into the end of the specific MachineBasicBlock, returning 337 // the number of instructions inserted. 338 unsigned RISCVInstrInfo::insertBranch( 339 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, 340 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { 341 if (BytesAdded) 342 *BytesAdded = 0; 343 344 // Shouldn't be a fall through. 345 assert(TBB && "insertBranch must not be told to insert a fallthrough"); 346 assert((Cond.size() == 3 || Cond.size() == 0) && 347 "RISCV branch conditions have two components!"); 348 349 // Unconditional branch. 350 if (Cond.empty()) { 351 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB); 352 if (BytesAdded) 353 *BytesAdded += getInstSizeInBytes(MI); 354 return 1; 355 } 356 357 // Either a one or two-way conditional branch. 358 unsigned Opc = Cond[0].getImm(); 359 MachineInstr &CondMI = 360 *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB); 361 if (BytesAdded) 362 *BytesAdded += getInstSizeInBytes(CondMI); 363 364 // One-way conditional branch. 365 if (!FBB) 366 return 1; 367 368 // Two-way conditional branch. 369 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB); 370 if (BytesAdded) 371 *BytesAdded += getInstSizeInBytes(MI); 372 return 2; 373 } 374 375 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, 376 MachineBasicBlock &DestBB, 377 const DebugLoc &DL, 378 int64_t BrOffset, 379 RegScavenger *RS) const { 380 assert(RS && "RegScavenger required for long branching"); 381 assert(MBB.empty() && 382 "new block should be inserted for expanding unconditional branch"); 383 assert(MBB.pred_size() == 1); 384 385 MachineFunction *MF = MBB.getParent(); 386 MachineRegisterInfo &MRI = MF->getRegInfo(); 387 388 if (!isInt<32>(BrOffset)) 389 report_fatal_error( 390 "Branch offsets outside of the signed 32-bit range not supported"); 391 392 // FIXME: A virtual register must be used initially, as the register 393 // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch 394 // uses the same workaround). 395 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 396 auto II = MBB.end(); 397 398 MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump)) 399 .addReg(ScratchReg, RegState::Define | RegState::Dead) 400 .addMBB(&DestBB, RISCVII::MO_CALL); 401 402 RS->enterBasicBlockEnd(MBB); 403 unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass, 404 MI.getIterator(), false, 0); 405 MRI.replaceRegWith(ScratchReg, Scav); 406 MRI.clearVirtRegs(); 407 RS->setRegUsed(Scav); 408 return 8; 409 } 410 411 bool RISCVInstrInfo::reverseBranchCondition( 412 SmallVectorImpl<MachineOperand> &Cond) const { 413 assert((Cond.size() == 3) && "Invalid branch condition!"); 414 Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm())); 415 return false; 416 } 417 418 MachineBasicBlock * 419 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { 420 assert(MI.getDesc().isBranch() && "Unexpected opcode!"); 421 // The branch target is always the last operand. 422 int NumOp = MI.getNumExplicitOperands(); 423 return MI.getOperand(NumOp - 1).getMBB(); 424 } 425 426 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp, 427 int64_t BrOffset) const { 428 unsigned XLen = STI.getXLen(); 429 // Ideally we could determine the supported branch offset from the 430 // RISCVII::FormMask, but this can't be used for Pseudo instructions like 431 // PseudoBR. 432 switch (BranchOp) { 433 default: 434 llvm_unreachable("Unexpected opcode!"); 435 case RISCV::BEQ: 436 case RISCV::BNE: 437 case RISCV::BLT: 438 case RISCV::BGE: 439 case RISCV::BLTU: 440 case RISCV::BGEU: 441 return isIntN(13, BrOffset); 442 case RISCV::JAL: 443 case RISCV::PseudoBR: 444 return isIntN(21, BrOffset); 445 case RISCV::PseudoJump: 446 return isIntN(32, SignExtend64(BrOffset + 0x800, XLen)); 447 } 448 } 449 450 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { 451 unsigned Opcode = MI.getOpcode(); 452 453 switch (Opcode) { 454 default: { 455 if (MI.getParent() && MI.getParent()->getParent()) { 456 const auto MF = MI.getMF(); 457 const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget()); 458 const MCRegisterInfo &MRI = *TM.getMCRegisterInfo(); 459 const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo(); 460 const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>(); 461 if (isCompressibleInst(MI, &ST, MRI, STI)) 462 return 2; 463 } 464 return get(Opcode).getSize(); 465 } 466 case TargetOpcode::EH_LABEL: 467 case TargetOpcode::IMPLICIT_DEF: 468 case TargetOpcode::KILL: 469 case TargetOpcode::DBG_VALUE: 470 return 0; 471 // These values are determined based on RISCVExpandAtomicPseudoInsts, 472 // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the 473 // pseudos are expanded. 474 case RISCV::PseudoCALLReg: 475 case RISCV::PseudoCALL: 476 case RISCV::PseudoJump: 477 case RISCV::PseudoTAIL: 478 case RISCV::PseudoLLA: 479 case RISCV::PseudoLA: 480 case RISCV::PseudoLA_TLS_IE: 481 case RISCV::PseudoLA_TLS_GD: 482 return 8; 483 case RISCV::PseudoAtomicLoadNand32: 484 case RISCV::PseudoAtomicLoadNand64: 485 return 20; 486 case RISCV::PseudoMaskedAtomicSwap32: 487 case RISCV::PseudoMaskedAtomicLoadAdd32: 488 case RISCV::PseudoMaskedAtomicLoadSub32: 489 return 28; 490 case RISCV::PseudoMaskedAtomicLoadNand32: 491 return 32; 492 case RISCV::PseudoMaskedAtomicLoadMax32: 493 case RISCV::PseudoMaskedAtomicLoadMin32: 494 return 44; 495 case RISCV::PseudoMaskedAtomicLoadUMax32: 496 case RISCV::PseudoMaskedAtomicLoadUMin32: 497 return 36; 498 case RISCV::PseudoCmpXchg32: 499 case RISCV::PseudoCmpXchg64: 500 return 16; 501 case RISCV::PseudoMaskedCmpXchg32: 502 return 32; 503 case TargetOpcode::INLINEASM: 504 case TargetOpcode::INLINEASM_BR: { 505 const MachineFunction &MF = *MI.getParent()->getParent(); 506 const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget()); 507 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), 508 *TM.getMCAsmInfo()); 509 } 510 } 511 } 512 513 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const { 514 const unsigned Opcode = MI.getOpcode(); 515 switch(Opcode) { 516 default: 517 break; 518 case RISCV::ADDI: 519 case RISCV::ORI: 520 case RISCV::XORI: 521 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0); 522 } 523 return MI.isAsCheapAsAMove(); 524 } 525 526 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, 527 StringRef &ErrInfo) const { 528 const MCInstrInfo *MCII = STI.getInstrInfo(); 529 MCInstrDesc const &Desc = MCII->get(MI.getOpcode()); 530 531 for (auto &OI : enumerate(Desc.operands())) { 532 unsigned OpType = OI.value().OperandType; 533 if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM && 534 OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) { 535 const MachineOperand &MO = MI.getOperand(OI.index()); 536 if (MO.isImm()) { 537 int64_t Imm = MO.getImm(); 538 bool Ok; 539 switch (OpType) { 540 default: 541 llvm_unreachable("Unexpected operand type"); 542 case RISCVOp::OPERAND_UIMM4: 543 Ok = isUInt<4>(Imm); 544 break; 545 case RISCVOp::OPERAND_UIMM5: 546 Ok = isUInt<5>(Imm); 547 break; 548 case RISCVOp::OPERAND_UIMM12: 549 Ok = isUInt<12>(Imm); 550 break; 551 case RISCVOp::OPERAND_SIMM12: 552 Ok = isInt<12>(Imm); 553 break; 554 case RISCVOp::OPERAND_SIMM13_LSB0: 555 Ok = isShiftedInt<12, 1>(Imm); 556 break; 557 case RISCVOp::OPERAND_UIMM20: 558 Ok = isUInt<20>(Imm); 559 break; 560 case RISCVOp::OPERAND_SIMM21_LSB0: 561 Ok = isShiftedInt<20, 1>(Imm); 562 break; 563 case RISCVOp::OPERAND_UIMMLOG2XLEN: 564 if (STI.getTargetTriple().isArch64Bit()) 565 Ok = isUInt<6>(Imm); 566 else 567 Ok = isUInt<5>(Imm); 568 break; 569 } 570 if (!Ok) { 571 ErrInfo = "Invalid immediate"; 572 return false; 573 } 574 } 575 } 576 } 577 578 return true; 579 } 580 581 // Return true if get the base operand, byte offset of an instruction and the 582 // memory width. Width is the size of memory that is being loaded/stored. 583 bool RISCVInstrInfo::getMemOperandWithOffsetWidth( 584 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, 585 unsigned &Width, const TargetRegisterInfo *TRI) const { 586 if (!LdSt.mayLoadOrStore()) 587 return false; 588 589 // Here we assume the standard RISC-V ISA, which uses a base+offset 590 // addressing mode. You'll need to relax these conditions to support custom 591 // load/stores instructions. 592 if (LdSt.getNumExplicitOperands() != 3) 593 return false; 594 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) 595 return false; 596 597 if (!LdSt.hasOneMemOperand()) 598 return false; 599 600 Width = (*LdSt.memoperands_begin())->getSize(); 601 BaseReg = &LdSt.getOperand(1); 602 Offset = LdSt.getOperand(2).getImm(); 603 return true; 604 } 605 606 bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint( 607 const MachineInstr &MIa, const MachineInstr &MIb) const { 608 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); 609 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); 610 611 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || 612 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) 613 return false; 614 615 // Retrieve the base register, offset from the base register and width. Width 616 // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If 617 // base registers are identical, and the offset of a lower memory access + 618 // the width doesn't overlap the offset of a higher memory access, 619 // then the memory accesses are different. 620 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); 621 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; 622 int64_t OffsetA = 0, OffsetB = 0; 623 unsigned int WidthA = 0, WidthB = 0; 624 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && 625 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { 626 if (BaseOpA->isIdenticalTo(*BaseOpB)) { 627 int LowOffset = std::min(OffsetA, OffsetB); 628 int HighOffset = std::max(OffsetA, OffsetB); 629 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB; 630 if (LowOffset + LowWidth <= HighOffset) 631 return true; 632 } 633 } 634 return false; 635 } 636 637 std::pair<unsigned, unsigned> 638 RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { 639 const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK; 640 return std::make_pair(TF & Mask, TF & ~Mask); 641 } 642 643 ArrayRef<std::pair<unsigned, const char *>> 644 RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { 645 using namespace RISCVII; 646 static const std::pair<unsigned, const char *> TargetFlags[] = { 647 {MO_CALL, "riscv-call"}, 648 {MO_PLT, "riscv-plt"}, 649 {MO_LO, "riscv-lo"}, 650 {MO_HI, "riscv-hi"}, 651 {MO_PCREL_LO, "riscv-pcrel-lo"}, 652 {MO_PCREL_HI, "riscv-pcrel-hi"}, 653 {MO_GOT_HI, "riscv-got-hi"}, 654 {MO_TPREL_LO, "riscv-tprel-lo"}, 655 {MO_TPREL_HI, "riscv-tprel-hi"}, 656 {MO_TPREL_ADD, "riscv-tprel-add"}, 657 {MO_TLS_GOT_HI, "riscv-tls-got-hi"}, 658 {MO_TLS_GD_HI, "riscv-tls-gd-hi"}}; 659 return makeArrayRef(TargetFlags); 660 } 661 bool RISCVInstrInfo::isFunctionSafeToOutlineFrom( 662 MachineFunction &MF, bool OutlineFromLinkOnceODRs) const { 663 const Function &F = MF.getFunction(); 664 665 // Can F be deduplicated by the linker? If it can, don't outline from it. 666 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage()) 667 return false; 668 669 // Don't outline from functions with section markings; the program could 670 // expect that all the code is in the named section. 671 if (F.hasSection()) 672 return false; 673 674 // It's safe to outline from MF. 675 return true; 676 } 677 678 bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 679 unsigned &Flags) const { 680 // More accurate safety checking is done in getOutliningCandidateInfo. 681 return true; 682 } 683 684 // Enum values indicating how an outlined call should be constructed. 685 enum MachineOutlinerConstructionID { 686 MachineOutlinerDefault 687 }; 688 689 outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo( 690 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const { 691 692 // First we need to filter out candidates where the X5 register (IE t0) can't 693 // be used to setup the function call. 694 auto CannotInsertCall = [](outliner::Candidate &C) { 695 const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo(); 696 697 C.initLRU(*TRI); 698 LiveRegUnits LRU = C.LRU; 699 return !LRU.available(RISCV::X5); 700 }; 701 702 RepeatedSequenceLocs.erase(std::remove_if(RepeatedSequenceLocs.begin(), 703 RepeatedSequenceLocs.end(), 704 CannotInsertCall), 705 RepeatedSequenceLocs.end()); 706 707 // If the sequence doesn't have enough candidates left, then we're done. 708 if (RepeatedSequenceLocs.size() < 2) 709 return outliner::OutlinedFunction(); 710 711 unsigned SequenceSize = 0; 712 713 auto I = RepeatedSequenceLocs[0].front(); 714 auto E = std::next(RepeatedSequenceLocs[0].back()); 715 for (; I != E; ++I) 716 SequenceSize += getInstSizeInBytes(*I); 717 718 // call t0, function = 8 bytes. 719 unsigned CallOverhead = 8; 720 for (auto &C : RepeatedSequenceLocs) 721 C.setCallInfo(MachineOutlinerDefault, CallOverhead); 722 723 // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled. 724 unsigned FrameOverhead = 4; 725 if (RepeatedSequenceLocs[0].getMF()->getSubtarget() 726 .getFeatureBits()[RISCV::FeatureStdExtC]) 727 FrameOverhead = 2; 728 729 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 730 FrameOverhead, MachineOutlinerDefault); 731 } 732 733 outliner::InstrType 734 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI, 735 unsigned Flags) const { 736 MachineInstr &MI = *MBBI; 737 MachineBasicBlock *MBB = MI.getParent(); 738 const TargetRegisterInfo *TRI = 739 MBB->getParent()->getSubtarget().getRegisterInfo(); 740 741 // Positions generally can't safely be outlined. 742 if (MI.isPosition()) { 743 // We can manually strip out CFI instructions later. 744 if (MI.isCFIInstruction()) 745 return outliner::InstrType::Invisible; 746 747 return outliner::InstrType::Illegal; 748 } 749 750 // Don't trust the user to write safe inline assembly. 751 if (MI.isInlineAsm()) 752 return outliner::InstrType::Illegal; 753 754 // We can't outline branches to other basic blocks. 755 if (MI.isTerminator() && !MBB->succ_empty()) 756 return outliner::InstrType::Illegal; 757 758 // We need support for tail calls to outlined functions before return 759 // statements can be allowed. 760 if (MI.isReturn()) 761 return outliner::InstrType::Illegal; 762 763 // Don't allow modifying the X5 register which we use for return addresses for 764 // these outlined functions. 765 if (MI.modifiesRegister(RISCV::X5, TRI) || 766 MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5)) 767 return outliner::InstrType::Illegal; 768 769 // Make sure the operands don't reference something unsafe. 770 for (const auto &MO : MI.operands()) 771 if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI()) 772 return outliner::InstrType::Illegal; 773 774 // Don't allow instructions which won't be materialized to impact outlining 775 // analysis. 776 if (MI.isMetaInstruction()) 777 return outliner::InstrType::Invisible; 778 779 return outliner::InstrType::Legal; 780 } 781 782 void RISCVInstrInfo::buildOutlinedFrame( 783 MachineBasicBlock &MBB, MachineFunction &MF, 784 const outliner::OutlinedFunction &OF) const { 785 786 // Strip out any CFI instructions 787 bool Changed = true; 788 while (Changed) { 789 Changed = false; 790 auto I = MBB.begin(); 791 auto E = MBB.end(); 792 for (; I != E; ++I) { 793 if (I->isCFIInstruction()) { 794 I->removeFromParent(); 795 Changed = true; 796 break; 797 } 798 } 799 } 800 801 MBB.addLiveIn(RISCV::X5); 802 803 // Add in a return instruction to the end of the outlined frame. 804 MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR)) 805 .addReg(RISCV::X0, RegState::Define) 806 .addReg(RISCV::X5) 807 .addImm(0)); 808 } 809 810 MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall( 811 Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, 812 MachineFunction &MF, const outliner::Candidate &C) const { 813 814 // Add in a call instruction to the outlined function at the given location. 815 It = MBB.insert(It, 816 BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5) 817 .addGlobalAddress(M.getNamedValue(MF.getName()), 0, 818 RISCVII::MO_CALL)); 819 return It; 820 } 821