xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (revision 2f513db72b034fd5ef7f080b11be5c711c15186a)
1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstrInfo.h"
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
16 #include "RISCVTargetMachine.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
25 
26 #define GET_INSTRINFO_CTOR_DTOR
27 #include "RISCVGenInstrInfo.inc"
28 
29 using namespace llvm;
30 
31 RISCVInstrInfo::RISCVInstrInfo()
32     : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP) {}
33 
34 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
35                                              int &FrameIndex) const {
36   switch (MI.getOpcode()) {
37   default:
38     return 0;
39   case RISCV::LB:
40   case RISCV::LBU:
41   case RISCV::LH:
42   case RISCV::LHU:
43   case RISCV::LW:
44   case RISCV::FLW:
45   case RISCV::LWU:
46   case RISCV::LD:
47   case RISCV::FLD:
48     break;
49   }
50 
51   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
52       MI.getOperand(2).getImm() == 0) {
53     FrameIndex = MI.getOperand(1).getIndex();
54     return MI.getOperand(0).getReg();
55   }
56 
57   return 0;
58 }
59 
60 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
61                                             int &FrameIndex) const {
62   switch (MI.getOpcode()) {
63   default:
64     return 0;
65   case RISCV::SB:
66   case RISCV::SH:
67   case RISCV::SW:
68   case RISCV::FSW:
69   case RISCV::SD:
70   case RISCV::FSD:
71     break;
72   }
73 
74   if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
75       MI.getOperand(1).getImm() == 0) {
76     FrameIndex = MI.getOperand(0).getIndex();
77     return MI.getOperand(2).getReg();
78   }
79 
80   return 0;
81 }
82 
83 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
84                                  MachineBasicBlock::iterator MBBI,
85                                  const DebugLoc &DL, unsigned DstReg,
86                                  unsigned SrcReg, bool KillSrc) const {
87   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
88     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
89         .addReg(SrcReg, getKillRegState(KillSrc))
90         .addImm(0);
91     return;
92   }
93 
94   // FPR->FPR copies
95   unsigned Opc;
96   if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
97     Opc = RISCV::FSGNJ_S;
98   else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
99     Opc = RISCV::FSGNJ_D;
100   else
101     llvm_unreachable("Impossible reg-to-reg copy");
102 
103   BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
104       .addReg(SrcReg, getKillRegState(KillSrc))
105       .addReg(SrcReg, getKillRegState(KillSrc));
106 }
107 
108 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
109                                          MachineBasicBlock::iterator I,
110                                          unsigned SrcReg, bool IsKill, int FI,
111                                          const TargetRegisterClass *RC,
112                                          const TargetRegisterInfo *TRI) const {
113   DebugLoc DL;
114   if (I != MBB.end())
115     DL = I->getDebugLoc();
116 
117   unsigned Opcode;
118 
119   if (RISCV::GPRRegClass.hasSubClassEq(RC))
120     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
121              RISCV::SW : RISCV::SD;
122   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
123     Opcode = RISCV::FSW;
124   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
125     Opcode = RISCV::FSD;
126   else
127     llvm_unreachable("Can't store this register to stack slot");
128 
129   BuildMI(MBB, I, DL, get(Opcode))
130       .addReg(SrcReg, getKillRegState(IsKill))
131       .addFrameIndex(FI)
132       .addImm(0);
133 }
134 
135 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
136                                           MachineBasicBlock::iterator I,
137                                           unsigned DstReg, int FI,
138                                           const TargetRegisterClass *RC,
139                                           const TargetRegisterInfo *TRI) const {
140   DebugLoc DL;
141   if (I != MBB.end())
142     DL = I->getDebugLoc();
143 
144   unsigned Opcode;
145 
146   if (RISCV::GPRRegClass.hasSubClassEq(RC))
147     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
148              RISCV::LW : RISCV::LD;
149   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
150     Opcode = RISCV::FLW;
151   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
152     Opcode = RISCV::FLD;
153   else
154     llvm_unreachable("Can't load this register from stack slot");
155 
156   BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
157 }
158 
159 void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
160                               MachineBasicBlock::iterator MBBI,
161                               const DebugLoc &DL, unsigned DstReg, uint64_t Val,
162                               MachineInstr::MIFlag Flag) const {
163   assert(isInt<32>(Val) && "Can only materialize 32-bit constants");
164 
165   // TODO: If the value can be materialized using only one instruction, only
166   // insert a single instruction.
167 
168   uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff;
169   uint64_t Lo12 = SignExtend64<12>(Val);
170   BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
171       .addImm(Hi20)
172       .setMIFlag(Flag);
173   BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
174       .addReg(DstReg, RegState::Kill)
175       .addImm(Lo12)
176       .setMIFlag(Flag);
177 }
178 
179 // The contents of values added to Cond are not examined outside of
180 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
181 // push BranchOpcode, Reg1, Reg2.
182 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
183                             SmallVectorImpl<MachineOperand> &Cond) {
184   // Block ends with fall-through condbranch.
185   assert(LastInst.getDesc().isConditionalBranch() &&
186          "Unknown conditional branch");
187   Target = LastInst.getOperand(2).getMBB();
188   Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
189   Cond.push_back(LastInst.getOperand(0));
190   Cond.push_back(LastInst.getOperand(1));
191 }
192 
193 static unsigned getOppositeBranchOpcode(int Opc) {
194   switch (Opc) {
195   default:
196     llvm_unreachable("Unrecognized conditional branch");
197   case RISCV::BEQ:
198     return RISCV::BNE;
199   case RISCV::BNE:
200     return RISCV::BEQ;
201   case RISCV::BLT:
202     return RISCV::BGE;
203   case RISCV::BGE:
204     return RISCV::BLT;
205   case RISCV::BLTU:
206     return RISCV::BGEU;
207   case RISCV::BGEU:
208     return RISCV::BLTU;
209   }
210 }
211 
212 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
213                                    MachineBasicBlock *&TBB,
214                                    MachineBasicBlock *&FBB,
215                                    SmallVectorImpl<MachineOperand> &Cond,
216                                    bool AllowModify) const {
217   TBB = FBB = nullptr;
218   Cond.clear();
219 
220   // If the block has no terminators, it just falls into the block after it.
221   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
222   if (I == MBB.end() || !isUnpredicatedTerminator(*I))
223     return false;
224 
225   // Count the number of terminators and find the first unconditional or
226   // indirect branch.
227   MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
228   int NumTerminators = 0;
229   for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
230        J++) {
231     NumTerminators++;
232     if (J->getDesc().isUnconditionalBranch() ||
233         J->getDesc().isIndirectBranch()) {
234       FirstUncondOrIndirectBr = J.getReverse();
235     }
236   }
237 
238   // If AllowModify is true, we can erase any terminators after
239   // FirstUncondOrIndirectBR.
240   if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
241     while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
242       std::next(FirstUncondOrIndirectBr)->eraseFromParent();
243       NumTerminators--;
244     }
245     I = FirstUncondOrIndirectBr;
246   }
247 
248   // We can't handle blocks that end in an indirect branch.
249   if (I->getDesc().isIndirectBranch())
250     return true;
251 
252   // We can't handle blocks with more than 2 terminators.
253   if (NumTerminators > 2)
254     return true;
255 
256   // Handle a single unconditional branch.
257   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
258     TBB = I->getOperand(0).getMBB();
259     return false;
260   }
261 
262   // Handle a single conditional branch.
263   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
264     parseCondBranch(*I, TBB, Cond);
265     return false;
266   }
267 
268   // Handle a conditional branch followed by an unconditional branch.
269   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
270       I->getDesc().isUnconditionalBranch()) {
271     parseCondBranch(*std::prev(I), TBB, Cond);
272     FBB = I->getOperand(0).getMBB();
273     return false;
274   }
275 
276   // Otherwise, we can't handle this.
277   return true;
278 }
279 
280 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
281                                       int *BytesRemoved) const {
282   if (BytesRemoved)
283     *BytesRemoved = 0;
284   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
285   if (I == MBB.end())
286     return 0;
287 
288   if (!I->getDesc().isUnconditionalBranch() &&
289       !I->getDesc().isConditionalBranch())
290     return 0;
291 
292   // Remove the branch.
293   if (BytesRemoved)
294     *BytesRemoved += getInstSizeInBytes(*I);
295   I->eraseFromParent();
296 
297   I = MBB.end();
298 
299   if (I == MBB.begin())
300     return 1;
301   --I;
302   if (!I->getDesc().isConditionalBranch())
303     return 1;
304 
305   // Remove the branch.
306   if (BytesRemoved)
307     *BytesRemoved += getInstSizeInBytes(*I);
308   I->eraseFromParent();
309   return 2;
310 }
311 
312 // Inserts a branch into the end of the specific MachineBasicBlock, returning
313 // the number of instructions inserted.
314 unsigned RISCVInstrInfo::insertBranch(
315     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
316     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
317   if (BytesAdded)
318     *BytesAdded = 0;
319 
320   // Shouldn't be a fall through.
321   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
322   assert((Cond.size() == 3 || Cond.size() == 0) &&
323          "RISCV branch conditions have two components!");
324 
325   // Unconditional branch.
326   if (Cond.empty()) {
327     MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
328     if (BytesAdded)
329       *BytesAdded += getInstSizeInBytes(MI);
330     return 1;
331   }
332 
333   // Either a one or two-way conditional branch.
334   unsigned Opc = Cond[0].getImm();
335   MachineInstr &CondMI =
336       *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
337   if (BytesAdded)
338     *BytesAdded += getInstSizeInBytes(CondMI);
339 
340   // One-way conditional branch.
341   if (!FBB)
342     return 1;
343 
344   // Two-way conditional branch.
345   MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
346   if (BytesAdded)
347     *BytesAdded += getInstSizeInBytes(MI);
348   return 2;
349 }
350 
351 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
352                                               MachineBasicBlock &DestBB,
353                                               const DebugLoc &DL,
354                                               int64_t BrOffset,
355                                               RegScavenger *RS) const {
356   assert(RS && "RegScavenger required for long branching");
357   assert(MBB.empty() &&
358          "new block should be inserted for expanding unconditional branch");
359   assert(MBB.pred_size() == 1);
360 
361   MachineFunction *MF = MBB.getParent();
362   MachineRegisterInfo &MRI = MF->getRegInfo();
363   const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
364 
365   if (TM.isPositionIndependent())
366     report_fatal_error("Unable to insert indirect branch");
367 
368   if (!isInt<32>(BrOffset))
369     report_fatal_error(
370         "Branch offsets outside of the signed 32-bit range not supported");
371 
372   // FIXME: A virtual register must be used initially, as the register
373   // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
374   // uses the same workaround).
375   unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
376   auto II = MBB.end();
377 
378   MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
379                              .addMBB(&DestBB, RISCVII::MO_HI);
380   BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
381       .addReg(ScratchReg, RegState::Kill)
382       .addMBB(&DestBB, RISCVII::MO_LO);
383 
384   RS->enterBasicBlockEnd(MBB);
385   unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
386                                                 LuiMI.getIterator(), false, 0);
387   MRI.replaceRegWith(ScratchReg, Scav);
388   MRI.clearVirtRegs();
389   RS->setRegUsed(Scav);
390   return 8;
391 }
392 
393 bool RISCVInstrInfo::reverseBranchCondition(
394     SmallVectorImpl<MachineOperand> &Cond) const {
395   assert((Cond.size() == 3) && "Invalid branch condition!");
396   Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
397   return false;
398 }
399 
400 MachineBasicBlock *
401 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
402   assert(MI.getDesc().isBranch() && "Unexpected opcode!");
403   // The branch target is always the last operand.
404   int NumOp = MI.getNumExplicitOperands();
405   return MI.getOperand(NumOp - 1).getMBB();
406 }
407 
408 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
409                                            int64_t BrOffset) const {
410   // Ideally we could determine the supported branch offset from the
411   // RISCVII::FormMask, but this can't be used for Pseudo instructions like
412   // PseudoBR.
413   switch (BranchOp) {
414   default:
415     llvm_unreachable("Unexpected opcode!");
416   case RISCV::BEQ:
417   case RISCV::BNE:
418   case RISCV::BLT:
419   case RISCV::BGE:
420   case RISCV::BLTU:
421   case RISCV::BGEU:
422     return isIntN(13, BrOffset);
423   case RISCV::JAL:
424   case RISCV::PseudoBR:
425     return isIntN(21, BrOffset);
426   }
427 }
428 
429 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
430   unsigned Opcode = MI.getOpcode();
431 
432   switch (Opcode) {
433   default: { return get(Opcode).getSize(); }
434   case TargetOpcode::EH_LABEL:
435   case TargetOpcode::IMPLICIT_DEF:
436   case TargetOpcode::KILL:
437   case TargetOpcode::DBG_VALUE:
438     return 0;
439   case RISCV::PseudoCALLReg:
440   case RISCV::PseudoCALL:
441   case RISCV::PseudoTAIL:
442   case RISCV::PseudoLLA:
443   case RISCV::PseudoLA:
444   case RISCV::PseudoLA_TLS_IE:
445   case RISCV::PseudoLA_TLS_GD:
446     return 8;
447   case TargetOpcode::INLINEASM:
448   case TargetOpcode::INLINEASM_BR: {
449     const MachineFunction &MF = *MI.getParent()->getParent();
450     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
451     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
452                               *TM.getMCAsmInfo());
453   }
454   }
455 }
456 
457 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
458   const unsigned Opcode = MI.getOpcode();
459   switch(Opcode) {
460     default:
461       break;
462     case RISCV::ADDI:
463     case RISCV::ORI:
464     case RISCV::XORI:
465       return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
466   }
467   return MI.isAsCheapAsAMove();
468 }
469