xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td (revision 2e3507c25e42292b45a5482e116d278f5515d04d) 
1//===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//  This file describes the RISC-V V extension instruction formats.
10//
11//===----------------------------------------------------------------------===//
12
13class RISCVVFormat<bits<3> val> {
14  bits<3> Value = val;
15}
16def OPIVV : RISCVVFormat<0b000>;
17def OPFVV : RISCVVFormat<0b001>;
18def OPMVV : RISCVVFormat<0b010>;
19def OPIVI : RISCVVFormat<0b011>;
20def OPIVX : RISCVVFormat<0b100>;
21def OPFVF : RISCVVFormat<0b101>;
22def OPMVX : RISCVVFormat<0b110>;
23def OPCFG : RISCVVFormat<0b111>;
24
25class RISCVMOP<bits<2> val> {
26  bits<2> Value = val;
27}
28def MOPLDUnitStride   : RISCVMOP<0b00>;
29def MOPLDIndexedUnord : RISCVMOP<0b01>;
30def MOPLDStrided      : RISCVMOP<0b10>;
31def MOPLDIndexedOrder : RISCVMOP<0b11>;
32
33def MOPSTUnitStride   : RISCVMOP<0b00>;
34def MOPSTIndexedUnord : RISCVMOP<0b01>;
35def MOPSTStrided      : RISCVMOP<0b10>;
36def MOPSTIndexedOrder : RISCVMOP<0b11>;
37
38class RISCVLSUMOP<bits<5> val> {
39  bits<5> Value = val;
40}
41def LUMOPUnitStride  : RISCVLSUMOP<0b00000>;
42def LUMOPUnitStrideMask : RISCVLSUMOP<0b01011>;
43def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
44def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
45def SUMOPUnitStride  : RISCVLSUMOP<0b00000>;
46def SUMOPUnitStrideMask : RISCVLSUMOP<0b01011>;
47def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
48
49class RISCVWidth<bits<4> val> {
50  bits<4> Value = val;
51}
52def LSWidth8     : RISCVWidth<0b0000>;
53def LSWidth16    : RISCVWidth<0b0101>;
54def LSWidth32    : RISCVWidth<0b0110>;
55def LSWidth64    : RISCVWidth<0b0111>;
56
57class RVInstSetiVLi<dag outs, dag ins, string opcodestr, string argstr>
58    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
59  bits<5> uimm;
60  bits<5> rd;
61  bits<10> vtypei;
62
63  let Inst{31} = 1;
64  let Inst{30} = 1;
65  let Inst{29-20} = vtypei{9-0};
66  let Inst{19-15} = uimm;
67  let Inst{14-12} = OPCFG.Value;
68  let Inst{11-7} = rd;
69  let Inst{6-0} = OPC_OP_V.Value;
70
71  let Defs = [VTYPE, VL];
72}
73
74class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
75    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
76  bits<5> rs1;
77  bits<5> rd;
78  bits<11> vtypei;
79
80  let Inst{31} = 0;
81  let Inst{30-20} = vtypei;
82  let Inst{19-15} = rs1;
83  let Inst{14-12} = OPCFG.Value;
84  let Inst{11-7} = rd;
85  let Inst{6-0} = OPC_OP_V.Value;
86
87  let Defs = [VTYPE, VL];
88}
89
90class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
91    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
92  bits<5> rs2;
93  bits<5> rs1;
94  bits<5> rd;
95
96  let Inst{31} = 1;
97  let Inst{30-25} = 0b000000;
98  let Inst{24-20} = rs2;
99  let Inst{19-15} = rs1;
100  let Inst{14-12} = OPCFG.Value;
101  let Inst{11-7} = rd;
102  let Inst{6-0} = OPC_OP_V.Value;
103
104  let Defs = [VTYPE, VL];
105}
106
107class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
108               string opcodestr, string argstr>
109    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
110  bits<5> vs2;
111  bits<5> vs1;
112  bits<5> vd;
113  bit vm;
114
115  let Inst{31-26} = funct6;
116  let Inst{25} = vm;
117  let Inst{24-20} = vs2;
118  let Inst{19-15} = vs1;
119  let Inst{14-12} = opv.Value;
120  let Inst{11-7} = vd;
121  let Inst{6-0} = OPC_OP_V.Value;
122
123  let Uses = [VTYPE, VL];
124  let RVVConstraint = VMConstraint;
125}
126
127class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
128                string opcodestr, string argstr>
129    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
130  bits<5> vs2;
131  bits<5> rs1;
132  bits<5> vd;
133  bit vm;
134
135  let Inst{31-26} = funct6;
136  let Inst{25} = vm;
137  let Inst{24-20} = vs2;
138  let Inst{19-15} = rs1;
139  let Inst{14-12} = opv.Value;
140  let Inst{11-7} = vd;
141  let Inst{6-0} = OPC_OP_V.Value;
142
143  let Uses = [VTYPE, VL];
144  let RVVConstraint = VMConstraint;
145}
146
147class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
148                string opcodestr, string argstr>
149    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
150  bits<5> rs1;
151  bits<5> vd;
152  bit vm;
153
154  let Inst{31-26} = funct6;
155  let Inst{25} = vm;
156  let Inst{24-20} = vs2;
157  let Inst{19-15} = rs1;
158  let Inst{14-12} = opv.Value;
159  let Inst{11-7} = vd;
160  let Inst{6-0} = OPC_OP_V.Value;
161
162  let Uses = [VTYPE, VL];
163  let RVVConstraint = VMConstraint;
164}
165
166class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
167                string argstr>
168    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
169  bits<5> vs2;
170  bits<5> imm;
171  bits<5> vd;
172  bit vm;
173
174  let Inst{31-26} = funct6;
175  let Inst{25} = vm;
176  let Inst{24-20} = vs2;
177  let Inst{19-15} = imm;
178  let Inst{14-12} = OPIVI.Value;
179  let Inst{11-7} = vd;
180  let Inst{6-0} = OPC_OP_V.Value;
181
182  let Uses = [VTYPE, VL];
183  let RVVConstraint = VMConstraint;
184}
185
186class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
187              dag ins, string opcodestr, string argstr>
188    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
189  bits<5> vs2;
190  bits<5> vd;
191  bit vm;
192
193  let Inst{31-26} = funct6;
194  let Inst{25} = vm;
195  let Inst{24-20} = vs2;
196  let Inst{19-15} = vs1;
197  let Inst{14-12} = opv.Value;
198  let Inst{11-7} = vd;
199  let Inst{6-0} = OPC_OP_V.Value;
200
201  let Uses = [VTYPE, VL];
202  let RVVConstraint = VMConstraint;
203}
204
205class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
206                bits<3> width, dag outs, dag ins, string opcodestr,
207                string argstr>
208    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
209  bits<5> rs1;
210  bits<5> vd;
211  bit vm;
212
213  let Inst{31-29} = nf;
214  let Inst{28} = mew;
215  let Inst{27-26} = MOPLDUnitStride.Value;
216  let Inst{25} = vm;
217  let Inst{24-20} = lumop.Value;
218  let Inst{19-15} = rs1;
219  let Inst{14-12} = width;
220  let Inst{11-7} = vd;
221  let Inst{6-0} = OPC_LOAD_FP.Value;
222
223  let Uses = [VTYPE, VL];
224  let RVVConstraint = VMConstraint;
225}
226
227class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
228                dag outs, dag ins, string opcodestr, string argstr>
229    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
230  bits<5> rs2;
231  bits<5> rs1;
232  bits<5> vd;
233  bit vm;
234
235  let Inst{31-29} = nf;
236  let Inst{28} = mew;
237  let Inst{27-26} = MOPLDStrided.Value;
238  let Inst{25} = vm;
239  let Inst{24-20} = rs2;
240  let Inst{19-15} = rs1;
241  let Inst{14-12} = width;
242  let Inst{11-7} = vd;
243  let Inst{6-0} = OPC_LOAD_FP.Value;
244
245  let Uses = [VTYPE, VL];
246  let RVVConstraint = VMConstraint;
247}
248
249class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
250                dag outs, dag ins, string opcodestr, string argstr>
251    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
252  bits<5> vs2;
253  bits<5> rs1;
254  bits<5> vd;
255  bit vm;
256
257  let Inst{31-29} = nf;
258  let Inst{28} = mew;
259  let Inst{27-26} = mop.Value;
260  let Inst{25} = vm;
261  let Inst{24-20} = vs2;
262  let Inst{19-15} = rs1;
263  let Inst{14-12} = width;
264  let Inst{11-7} = vd;
265  let Inst{6-0} = OPC_LOAD_FP.Value;
266
267  let Uses = [VTYPE, VL];
268  let RVVConstraint = VMConstraint;
269}
270
271class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
272                bits<3> width, dag outs, dag ins, string opcodestr,
273                string argstr>
274    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
275  bits<5> rs1;
276  bits<5> vs3;
277  bit vm;
278
279  let Inst{31-29} = nf;
280  let Inst{28} = mew;
281  let Inst{27-26} = MOPSTUnitStride.Value;
282  let Inst{25} = vm;
283  let Inst{24-20} = sumop.Value;
284  let Inst{19-15} = rs1;
285  let Inst{14-12} = width;
286  let Inst{11-7} = vs3;
287  let Inst{6-0} = OPC_STORE_FP.Value;
288
289  let Uses = [VTYPE, VL];
290}
291
292class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
293                dag outs, dag ins, string opcodestr, string argstr>
294    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
295  bits<5> rs2;
296  bits<5> rs1;
297  bits<5> vs3;
298  bit vm;
299
300  let Inst{31-29} = nf;
301  let Inst{28} = mew;
302  let Inst{27-26} = MOPSTStrided.Value;
303  let Inst{25} = vm;
304  let Inst{24-20} = rs2;
305  let Inst{19-15} = rs1;
306  let Inst{14-12} = width;
307  let Inst{11-7} = vs3;
308  let Inst{6-0} = OPC_STORE_FP.Value;
309
310  let Uses = [VTYPE, VL];
311}
312
313class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
314                dag outs, dag ins, string opcodestr, string argstr>
315    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
316  bits<5> vs2;
317  bits<5> rs1;
318  bits<5> vs3;
319  bit vm;
320
321  let Inst{31-29} = nf;
322  let Inst{28} = mew;
323  let Inst{27-26} = mop.Value;
324  let Inst{25} = vm;
325  let Inst{24-20} = vs2;
326  let Inst{19-15} = rs1;
327  let Inst{14-12} = width;
328  let Inst{11-7} = vs3;
329  let Inst{6-0} = OPC_STORE_FP.Value;
330
331  let Uses = [VTYPE, VL];
332}
333