1//===-- RISCVInstrFormatsV.td - RISCV V Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V V extension instruction formats. 10// 11//===----------------------------------------------------------------------===// 12 13class RISCVVFormat<bits<3> val> { 14 bits<3> Value = val; 15} 16def OPIVV : RISCVVFormat<0b000>; 17def OPFVV : RISCVVFormat<0b001>; 18def OPMVV : RISCVVFormat<0b010>; 19def OPIVI : RISCVVFormat<0b011>; 20def OPIVX : RISCVVFormat<0b100>; 21def OPFVF : RISCVVFormat<0b101>; 22def OPMVX : RISCVVFormat<0b110>; 23 24class RISCVMOP<bits<2> val> { 25 bits<2> Value = val; 26} 27def MOPLDUnitStride : RISCVMOP<0b00>; 28def MOPLDIndexedUnord : RISCVMOP<0b01>; 29def MOPLDStrided : RISCVMOP<0b10>; 30def MOPLDIndexedOrder : RISCVMOP<0b11>; 31 32def MOPSTUnitStride : RISCVMOP<0b00>; 33def MOPSTIndexedUnord : RISCVMOP<0b01>; 34def MOPSTStrided : RISCVMOP<0b10>; 35def MOPSTIndexedOrder : RISCVMOP<0b11>; 36 37class RISCVLSUMOP<bits<5> val> { 38 bits<5> Value = val; 39} 40def LUMOPUnitStride : RISCVLSUMOP<0b00000>; 41def LUMOPUnitStrideMask : RISCVLSUMOP<0b01011>; 42def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>; 43def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>; 44def SUMOPUnitStride : RISCVLSUMOP<0b00000>; 45def SUMOPUnitStrideMask : RISCVLSUMOP<0b01011>; 46def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>; 47 48class RISCVWidth<bits<4> val> { 49 bits<4> Value = val; 50} 51def LSWidth8 : RISCVWidth<0b0000>; 52def LSWidth16 : RISCVWidth<0b0101>; 53def LSWidth32 : RISCVWidth<0b0110>; 54def LSWidth64 : RISCVWidth<0b0111>; 55 56class RVInstSetiVLi<dag outs, dag ins, string opcodestr, string argstr> 57 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 58 bits<5> uimm; 59 bits<5> rd; 60 bits<10> vtypei; 61 62 let Inst{31} = 1; 63 let Inst{30} = 1; 64 let Inst{29-20} = vtypei{9-0}; 65 let Inst{19-15} = uimm; 66 let Inst{14-12} = 0b111; 67 let Inst{11-7} = rd; 68 let Opcode = OPC_OP_V.Value; 69 70 let Defs = [VTYPE, VL]; 71} 72 73class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr> 74 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 75 bits<5> rs1; 76 bits<5> rd; 77 bits<11> vtypei; 78 79 let Inst{31} = 0; 80 let Inst{30-20} = vtypei; 81 let Inst{19-15} = rs1; 82 let Inst{14-12} = 0b111; 83 let Inst{11-7} = rd; 84 let Opcode = OPC_OP_V.Value; 85 86 let Defs = [VTYPE, VL]; 87} 88 89class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr> 90 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 91 bits<5> rs2; 92 bits<5> rs1; 93 bits<5> rd; 94 95 let Inst{31} = 1; 96 let Inst{30-25} = 0b000000; 97 let Inst{24-20} = rs2; 98 let Inst{19-15} = rs1; 99 let Inst{14-12} = 0b111; 100 let Inst{11-7} = rd; 101 let Opcode = OPC_OP_V.Value; 102 103 let Defs = [VTYPE, VL]; 104} 105 106class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins, 107 string opcodestr, string argstr> 108 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 109 bits<5> vs2; 110 bits<5> vs1; 111 bits<5> vd; 112 bit vm; 113 114 let Inst{31-26} = funct6; 115 let Inst{25} = vm; 116 let Inst{24-20} = vs2; 117 let Inst{19-15} = vs1; 118 let Inst{14-12} = opv.Value; 119 let Inst{11-7} = vd; 120 let Opcode = OPC_OP_V.Value; 121 122 let Uses = [VTYPE, VL]; 123 let RVVConstraint = VMConstraint; 124} 125 126class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins, 127 string opcodestr, string argstr> 128 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 129 bits<5> vs2; 130 bits<5> rs1; 131 bits<5> vd; 132 bit vm; 133 134 let Inst{31-26} = funct6; 135 let Inst{25} = vm; 136 let Inst{24-20} = vs2; 137 let Inst{19-15} = rs1; 138 let Inst{14-12} = opv.Value; 139 let Inst{11-7} = vd; 140 let Opcode = OPC_OP_V.Value; 141 142 let Uses = [VTYPE, VL]; 143 let RVVConstraint = VMConstraint; 144} 145 146class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins, 147 string opcodestr, string argstr> 148 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 149 bits<5> rs1; 150 bits<5> vd; 151 bit vm; 152 153 let Inst{31-26} = funct6; 154 let Inst{25} = vm; 155 let Inst{24-20} = vs2; 156 let Inst{19-15} = rs1; 157 let Inst{14-12} = opv.Value; 158 let Inst{11-7} = vd; 159 let Opcode = OPC_OP_V.Value; 160 161 let Uses = [VTYPE, VL]; 162 let RVVConstraint = VMConstraint; 163} 164 165class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr, 166 string argstr> 167 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 168 bits<5> vs2; 169 bits<5> imm; 170 bits<5> vd; 171 bit vm; 172 173 let Inst{31-26} = funct6; 174 let Inst{25} = vm; 175 let Inst{24-20} = vs2; 176 let Inst{19-15} = imm; 177 let Inst{14-12} = 0b011; 178 let Inst{11-7} = vd; 179 let Opcode = OPC_OP_V.Value; 180 181 let Uses = [VTYPE, VL]; 182 let RVVConstraint = VMConstraint; 183} 184 185class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs, 186 dag ins, string opcodestr, string argstr> 187 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 188 bits<5> vs2; 189 bits<5> vd; 190 bit vm; 191 192 let Inst{31-26} = funct6; 193 let Inst{25} = vm; 194 let Inst{24-20} = vs2; 195 let Inst{19-15} = vs1; 196 let Inst{14-12} = opv.Value; 197 let Inst{11-7} = vd; 198 let Opcode = OPC_OP_V.Value; 199 200 let Uses = [VTYPE, VL]; 201 let RVVConstraint = VMConstraint; 202} 203 204class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop, 205 bits<3> width, dag outs, dag ins, string opcodestr, 206 string argstr> 207 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 208 bits<5> rs1; 209 bits<5> vd; 210 bit vm; 211 212 let Inst{31-29} = nf; 213 let Inst{28} = mew; 214 let Inst{27-26} = MOPLDUnitStride.Value; 215 let Inst{25} = vm; 216 let Inst{24-20} = lumop.Value; 217 let Inst{19-15} = rs1; 218 let Inst{14-12} = width; 219 let Inst{11-7} = vd; 220 let Opcode = OPC_LOAD_FP.Value; 221 222 let Uses = [VTYPE, VL]; 223 let RVVConstraint = VMConstraint; 224} 225 226class RVInstVLS<bits<3> nf, bit mew, bits<3> width, 227 dag outs, dag ins, string opcodestr, string argstr> 228 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 229 bits<5> rs2; 230 bits<5> rs1; 231 bits<5> vd; 232 bit vm; 233 234 let Inst{31-29} = nf; 235 let Inst{28} = mew; 236 let Inst{27-26} = MOPLDStrided.Value; 237 let Inst{25} = vm; 238 let Inst{24-20} = rs2; 239 let Inst{19-15} = rs1; 240 let Inst{14-12} = width; 241 let Inst{11-7} = vd; 242 let Opcode = OPC_LOAD_FP.Value; 243 244 let Uses = [VTYPE, VL]; 245 let RVVConstraint = VMConstraint; 246} 247 248class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width, 249 dag outs, dag ins, string opcodestr, string argstr> 250 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 251 bits<5> vs2; 252 bits<5> rs1; 253 bits<5> vd; 254 bit vm; 255 256 let Inst{31-29} = nf; 257 let Inst{28} = mew; 258 let Inst{27-26} = mop.Value; 259 let Inst{25} = vm; 260 let Inst{24-20} = vs2; 261 let Inst{19-15} = rs1; 262 let Inst{14-12} = width; 263 let Inst{11-7} = vd; 264 let Opcode = OPC_LOAD_FP.Value; 265 266 let Uses = [VTYPE, VL]; 267 let RVVConstraint = VMConstraint; 268} 269 270class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop, 271 bits<3> width, dag outs, dag ins, string opcodestr, 272 string argstr> 273 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 274 bits<5> rs1; 275 bits<5> vs3; 276 bit vm; 277 278 let Inst{31-29} = nf; 279 let Inst{28} = mew; 280 let Inst{27-26} = MOPSTUnitStride.Value; 281 let Inst{25} = vm; 282 let Inst{24-20} = sumop.Value; 283 let Inst{19-15} = rs1; 284 let Inst{14-12} = width; 285 let Inst{11-7} = vs3; 286 let Opcode = OPC_STORE_FP.Value; 287 288 let Uses = [VTYPE, VL]; 289} 290 291class RVInstVSS<bits<3> nf, bit mew, bits<3> width, 292 dag outs, dag ins, string opcodestr, string argstr> 293 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 294 bits<5> rs2; 295 bits<5> rs1; 296 bits<5> vs3; 297 bit vm; 298 299 let Inst{31-29} = nf; 300 let Inst{28} = mew; 301 let Inst{27-26} = MOPSTStrided.Value; 302 let Inst{25} = vm; 303 let Inst{24-20} = rs2; 304 let Inst{19-15} = rs1; 305 let Inst{14-12} = width; 306 let Inst{11-7} = vs3; 307 let Opcode = OPC_STORE_FP.Value; 308 309 let Uses = [VTYPE, VL]; 310} 311 312class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width, 313 dag outs, dag ins, string opcodestr, string argstr> 314 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 315 bits<5> vs2; 316 bits<5> rs1; 317 bits<5> vs3; 318 bit vm; 319 320 let Inst{31-29} = nf; 321 let Inst{28} = mew; 322 let Inst{27-26} = mop.Value; 323 let Inst{25} = vm; 324 let Inst{24-20} = vs2; 325 let Inst{19-15} = rs1; 326 let Inst{14-12} = width; 327 let Inst{11-7} = vs3; 328 let Opcode = OPC_STORE_FP.Value; 329 330 let Uses = [VTYPE, VL]; 331} 332