1//===-- RISCVInstrFormatsC.td - RISCV C Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V C extension instruction formats. 10// 11//===----------------------------------------------------------------------===// 12 13class RVInst16<dag outs, dag ins, string opcodestr, string argstr, 14 list<dag> pattern, InstFormat format> 15 : Instruction { 16 field bits<16> Inst; 17 // SoftFail is a field the disassembler can use to provide a way for 18 // instructions to not match without killing the whole decode process. It is 19 // mainly used for ARM, but Tablegen expects this field to exist or it fails 20 // to build the decode table. 21 field bits<16> SoftFail = 0; 22 let Size = 2; 23 24 bits<2> Opcode = 0; 25 26 let Namespace = "RISCV"; 27 28 dag OutOperandList = outs; 29 dag InOperandList = ins; 30 let AsmString = opcodestr # "\t" # argstr; 31 let Pattern = pattern; 32 33 let TSFlags{4-0} = format.Value; 34} 35 36class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins, 37 string opcodestr, string argstr> 38 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCR> { 39 bits<5> rs1; 40 bits<5> rs2; 41 42 let Inst{15-12} = funct4; 43 let Inst{11-7} = rs1; 44 let Inst{6-2} = rs2; 45 let Inst{1-0} = opcode; 46} 47 48// The immediate value encoding differs for each instruction, so each subclass 49// is responsible for setting the appropriate bits in the Inst field. 50// The bits Inst{6-2} must be set for each instruction. 51class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 52 string opcodestr, string argstr> 53 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCI> { 54 bits<10> imm; 55 bits<5> rd; 56 bits<5> rs1; 57 58 let Inst{15-13} = funct3; 59 let Inst{12} = imm{5}; 60 let Inst{11-7} = rd; 61 let Inst{1-0} = opcode; 62} 63 64// The immediate value encoding differs for each instruction, so each subclass 65// is responsible for setting the appropriate bits in the Inst field. 66// The bits Inst{12-7} must be set for each instruction. 67class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 68 string opcodestr, string argstr> 69 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSS> { 70 bits<10> imm; 71 bits<5> rs2; 72 bits<5> rs1; 73 74 let Inst{15-13} = funct3; 75 let Inst{6-2} = rs2; 76 let Inst{1-0} = opcode; 77} 78 79class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 80 string opcodestr, string argstr> 81 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCIW> { 82 bits<10> imm; 83 bits<3> rd; 84 85 let Inst{15-13} = funct3; 86 let Inst{4-2} = rd; 87 let Inst{1-0} = opcode; 88} 89 90// The immediate value encoding differs for each instruction, so each subclass 91// is responsible for setting the appropriate bits in the Inst field. 92// The bits Inst{12-10} and Inst{6-5} must be set for each instruction. 93class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 94 string opcodestr, string argstr> 95 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCL> { 96 bits<3> rd; 97 bits<3> rs1; 98 99 let Inst{15-13} = funct3; 100 let Inst{9-7} = rs1; 101 let Inst{4-2} = rd; 102 let Inst{1-0} = opcode; 103} 104 105// The immediate value encoding differs for each instruction, so each subclass 106// is responsible for setting the appropriate bits in the Inst field. 107// The bits Inst{12-10} and Inst{6-5} must be set for each instruction. 108class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 109 string opcodestr, string argstr> 110 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCS> { 111 bits<3> rs2; 112 bits<3> rs1; 113 114 let Inst{15-13} = funct3; 115 let Inst{9-7} = rs1; 116 let Inst{4-2} = rs2; 117 let Inst{1-0} = opcode; 118} 119 120class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs, 121 dag ins, string opcodestr, string argstr> 122 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCA> { 123 bits<3> rs2; 124 bits<3> rs1; 125 126 let Inst{15-10} = funct6; 127 let Inst{9-7} = rs1; 128 let Inst{6-5} = funct2; 129 let Inst{4-2} = rs2; 130 let Inst{1-0} = opcode; 131} 132 133class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 134 string opcodestr, string argstr> 135 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> { 136 bits<9> imm; 137 bits<3> rs1; 138 139 let Inst{15-13} = funct3; 140 let Inst{9-7} = rs1; 141 let Inst{1-0} = opcode; 142} 143 144class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 145 string opcodestr, string argstr> 146 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCJ> { 147 bits<11> offset; 148 149 let Inst{15-13} = funct3; 150 let Inst{12} = offset{10}; 151 let Inst{11} = offset{3}; 152 let Inst{10-9} = offset{8-7}; 153 let Inst{8} = offset{9}; 154 let Inst{7} = offset{5}; 155 let Inst{6} = offset{6}; 156 let Inst{5-3} = offset{2-0}; 157 let Inst{2} = offset{4}; 158 let Inst{1-0} = opcode; 159} 160