1//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// These instruction format definitions are structured to match the 12// description in the RISC-V User-Level ISA specification as closely as 13// possible. For instance, the specification describes instructions with the 14// MSB (31st bit) on the left and the LSB (0th bit) on the right. This is 15// reflected in the order of parameters to each instruction class. 16// 17// One area of divergence is in the description of immediates. The 18// specification describes immediate encoding in terms of bit-slicing 19// operations on the logical value represented. The immediate argument to 20// these instruction formats instead represents the bit sequence that will be 21// inserted into the instruction. e.g. although JAL's immediate is logically 22// a 21-bit value (where the LSB is always zero), we describe it as an imm20 23// to match how it is encoded. 24// 25//===----------------------------------------------------------------------===// 26 27// Format specifies the encoding used by the instruction. This is used by 28// RISCVMCCodeEmitter to determine which form of fixup to use. These 29// definitions must be kept in-sync with RISCVBaseInfo.h. 30class InstFormat<bits<5> val> { 31 bits<5> Value = val; 32} 33def InstFormatPseudo : InstFormat<0>; 34def InstFormatR : InstFormat<1>; 35def InstFormatR4 : InstFormat<2>; 36def InstFormatI : InstFormat<3>; 37def InstFormatS : InstFormat<4>; 38def InstFormatB : InstFormat<5>; 39def InstFormatU : InstFormat<6>; 40def InstFormatJ : InstFormat<7>; 41def InstFormatCR : InstFormat<8>; 42def InstFormatCI : InstFormat<9>; 43def InstFormatCSS : InstFormat<10>; 44def InstFormatCIW : InstFormat<11>; 45def InstFormatCL : InstFormat<12>; 46def InstFormatCS : InstFormat<13>; 47def InstFormatCA : InstFormat<14>; 48def InstFormatCB : InstFormat<15>; 49def InstFormatCJ : InstFormat<16>; 50def InstFormatOther : InstFormat<17>; 51 52class RISCVVConstraint<bits<3> val> { 53 bits<3> Value = val; 54} 55def NoConstraint : RISCVVConstraint<0b000>; 56def VS2Constraint : RISCVVConstraint<0b001>; 57def VS1Constraint : RISCVVConstraint<0b010>; 58def VMConstraint : RISCVVConstraint<0b100>; 59 60// Illegal instructions: 61// 62// * The destination vector register group for a masked vector instruction 63// cannot overlap the source mask register (v0), unless the destination vector 64// register is being written with a mask value (e.g., comparisons) or the 65// scalar result of a reduction. 66// 67// * Widening: The destination EEW is greater than the source EEW, the source 68// EMUL is at least 1. The destination vector register group cannot overlap 69// with the source vector register groups besides the highest-numbered part of 70// the destination register group. 71// 72// * Narrowing: The destination EEW is smaller than the source EEW. The 73// destination vector register group cannot overlap with the source vector 74// register groups besides the lowest-numbered part of the source register 75// group. 76// 77// * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the 78// source register and, if masked, cannot overlap the mask register ('v0'). 79// 80// * viota: The destination register cannot overlap the source register and, 81// if masked, cannot overlap the mask register ('v0'). 82// 83// * v[f]slide[1]up: The destination vector register group for vslideup cannot 84// overlap the source vector register group. 85// 86// * vrgather: The destination vector register group cannot overlap with the 87// source vector register groups. 88// 89// * vcompress: The destination vector register group cannot overlap the 90// source vector register group or the source mask register 91def WidenV : RISCVVConstraint<!or(VS2Constraint.Value, 92 VS1Constraint.Value, 93 VMConstraint.Value)>; 94def WidenW : RISCVVConstraint<!or(VS1Constraint.Value, 95 VMConstraint.Value)>; 96def WidenCvt : RISCVVConstraint<!or(VS2Constraint.Value, 97 VMConstraint.Value)>; 98def Iota : RISCVVConstraint<!or(VS2Constraint.Value, 99 VMConstraint.Value)>; 100def SlideUp : RISCVVConstraint<!or(VS2Constraint.Value, 101 VMConstraint.Value)>; 102def Vrgather : RISCVVConstraint<!or(VS2Constraint.Value, 103 VS1Constraint.Value, 104 VMConstraint.Value)>; 105def Vcompress : RISCVVConstraint<!or(VS2Constraint.Value, 106 VS1Constraint.Value)>; 107 108// The following opcode names match those given in Table 19.1 in the 109// RISC-V User-level ISA specification ("RISC-V base opcode map"). 110class RISCVOpcode<string name, bits<7> val> { 111 string Name = name; 112 bits<7> Value = val; 113} 114def RISCVOpcodesList : GenericTable { 115 let FilterClass = "RISCVOpcode"; 116 let Fields = [ 117 "Name", "Value" 118 ]; 119 let PrimaryKey = [ "Value" ]; 120 let PrimaryKeyName = "lookupRISCVOpcodeByValue"; 121} 122def lookupRISCVOpcodeByName : SearchIndex { 123 let Table = RISCVOpcodesList; 124 let Key = [ "Name" ]; 125} 126def OPC_LOAD : RISCVOpcode<"LOAD", 0b0000011>; 127def OPC_LOAD_FP : RISCVOpcode<"LOAD_FP", 0b0000111>; 128def OPC_MISC_MEM : RISCVOpcode<"MISC_MEM", 0b0001111>; 129def OPC_OP_IMM : RISCVOpcode<"OP_IMM", 0b0010011>; 130def OPC_AUIPC : RISCVOpcode<"AUIPC", 0b0010111>; 131def OPC_OP_IMM_32 : RISCVOpcode<"OP_IMM_32", 0b0011011>; 132def OPC_STORE : RISCVOpcode<"STORE", 0b0100011>; 133def OPC_STORE_FP : RISCVOpcode<"STORE_FP", 0b0100111>; 134def OPC_AMO : RISCVOpcode<"AMO", 0b0101111>; 135def OPC_OP : RISCVOpcode<"OP", 0b0110011>; 136def OPC_LUI : RISCVOpcode<"LUI", 0b0110111>; 137def OPC_OP_32 : RISCVOpcode<"OP_32", 0b0111011>; 138def OPC_MADD : RISCVOpcode<"MADD", 0b1000011>; 139def OPC_MSUB : RISCVOpcode<"MSUB", 0b1000111>; 140def OPC_NMSUB : RISCVOpcode<"NMSUB", 0b1001011>; 141def OPC_NMADD : RISCVOpcode<"NMADD", 0b1001111>; 142def OPC_OP_FP : RISCVOpcode<"OP_FP", 0b1010011>; 143def OPC_OP_V : RISCVOpcode<"OP_V", 0b1010111>; 144def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>; 145def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>; 146def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>; 147def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>; 148 149class RVInst<dag outs, dag ins, string opcodestr, string argstr, 150 list<dag> pattern, InstFormat format> 151 : Instruction { 152 field bits<32> Inst; 153 // SoftFail is a field the disassembler can use to provide a way for 154 // instructions to not match without killing the whole decode process. It is 155 // mainly used for ARM, but Tablegen expects this field to exist or it fails 156 // to build the decode table. 157 field bits<32> SoftFail = 0; 158 let Size = 4; 159 160 bits<7> Opcode = 0; 161 162 let Inst{6-0} = Opcode; 163 164 let Namespace = "RISCV"; 165 166 dag OutOperandList = outs; 167 dag InOperandList = ins; 168 let AsmString = opcodestr # "\t" # argstr; 169 let Pattern = pattern; 170 171 let TSFlags{4-0} = format.Value; 172 173 // Defaults 174 RISCVVConstraint RVVConstraint = NoConstraint; 175 let TSFlags{7-5} = RVVConstraint.Value; 176 177 bits<3> VLMul = 0; 178 let TSFlags{10-8} = VLMul; 179 180 bit HasDummyMask = 0; 181 let TSFlags{11} = HasDummyMask; 182 183 bit ForceTailAgnostic = false; 184 let TSFlags{12} = ForceTailAgnostic; 185 186 bit HasMergeOp = 0; 187 let TSFlags{13} = HasMergeOp; 188 189 bit HasSEWOp = 0; 190 let TSFlags{14} = HasSEWOp; 191 192 bit HasVLOp = 0; 193 let TSFlags{15} = HasVLOp; 194 195 bit HasVecPolicyOp = 0; 196 let TSFlags{16} = HasVecPolicyOp; 197 198 bit IsRVVWideningReduction = 0; 199 let TSFlags{17} = IsRVVWideningReduction; 200} 201 202// Pseudo instructions 203class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = ""> 204 : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> { 205 let isPseudo = 1; 206 let isCodeGenOnly = 1; 207} 208 209class PseudoQuietFCMP<RegisterClass Ty> 210 : Pseudo<(outs GPR:$rd), (ins Ty:$rs1, Ty:$rs2), []> { 211 let hasSideEffects = 1; 212 let mayLoad = 0; 213 let mayStore = 0; 214} 215 216// Pseudo load instructions. 217class PseudoLoad<string opcodestr, RegisterClass rdty = GPR> 218 : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> { 219 let hasSideEffects = 0; 220 let mayLoad = 1; 221 let mayStore = 0; 222 let isCodeGenOnly = 0; 223 let isAsmParserOnly = 1; 224} 225 226class PseudoFloatLoad<string opcodestr, RegisterClass rdty = GPR> 227 : Pseudo<(outs GPR:$tmp, rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> { 228 let hasSideEffects = 0; 229 let mayLoad = 1; 230 let mayStore = 0; 231 let isCodeGenOnly = 0; 232 let isAsmParserOnly = 1; 233} 234 235// Pseudo store instructions. 236class PseudoStore<string opcodestr, RegisterClass rsty = GPR> 237 : Pseudo<(outs GPR:$tmp), (ins rsty:$rs, bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> { 238 let hasSideEffects = 0; 239 let mayLoad = 0; 240 let mayStore = 1; 241 let isCodeGenOnly = 0; 242 let isAsmParserOnly = 1; 243} 244 245// Instruction formats are listed in the order they appear in the RISC-V 246// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4, 247// RVInstRAtomic) sorted alphabetically. 248 249class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs, 250 dag ins, string opcodestr, string argstr> 251 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 252 bits<5> rs2; 253 bits<5> rs1; 254 bits<5> rd; 255 256 let Inst{31-25} = funct7; 257 let Inst{24-20} = rs2; 258 let Inst{19-15} = rs1; 259 let Inst{14-12} = funct3; 260 let Inst{11-7} = rd; 261 let Opcode = opcode.Value; 262} 263 264class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs, 265 dag ins, string opcodestr, string argstr> 266 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> { 267 bits<5> rs3; 268 bits<5> rs2; 269 bits<5> rs1; 270 bits<5> rd; 271 272 let Inst{31-27} = rs3; 273 let Inst{26-25} = funct2; 274 let Inst{24-20} = rs2; 275 let Inst{19-15} = rs1; 276 let Inst{14-12} = funct3; 277 let Inst{11-7} = rd; 278 let Opcode = opcode.Value; 279} 280 281class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins, 282 string opcodestr, string argstr> 283 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> { 284 bits<5> rs3; 285 bits<5> rs2; 286 bits<5> rs1; 287 bits<3> frm; 288 bits<5> rd; 289 290 let Inst{31-27} = rs3; 291 let Inst{26-25} = funct2; 292 let Inst{24-20} = rs2; 293 let Inst{19-15} = rs1; 294 let Inst{14-12} = frm; 295 let Inst{11-7} = rd; 296 let Opcode = opcode.Value; 297} 298 299class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3, 300 RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 301 string argstr> 302 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 303 bits<5> rs2; 304 bits<5> rs1; 305 bits<5> rd; 306 307 let Inst{31-27} = funct5; 308 let Inst{26} = aq; 309 let Inst{25} = rl; 310 let Inst{24-20} = rs2; 311 let Inst{19-15} = rs1; 312 let Inst{14-12} = funct3; 313 let Inst{11-7} = rd; 314 let Opcode = opcode.Value; 315} 316 317class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins, 318 string opcodestr, string argstr> 319 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 320 bits<5> rs2; 321 bits<5> rs1; 322 bits<3> frm; 323 bits<5> rd; 324 325 let Inst{31-25} = funct7; 326 let Inst{24-20} = rs2; 327 let Inst{19-15} = rs1; 328 let Inst{14-12} = frm; 329 let Inst{11-7} = rd; 330 let Opcode = opcode.Value; 331} 332 333class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 334 string opcodestr, string argstr> 335 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 336 bits<12> imm12; 337 bits<5> rs1; 338 bits<5> rd; 339 340 let Inst{31-20} = imm12; 341 let Inst{19-15} = rs1; 342 let Inst{14-12} = funct3; 343 let Inst{11-7} = rd; 344 let Opcode = opcode.Value; 345} 346 347class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode, 348 dag outs, dag ins, string opcodestr, string argstr> 349 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 350 bits<6> shamt; 351 bits<5> rs1; 352 bits<5> rd; 353 354 let Inst{31-27} = imm11_7; 355 let Inst{26} = 0; 356 let Inst{25-20} = shamt; 357 let Inst{19-15} = rs1; 358 let Inst{14-12} = funct3; 359 let Inst{11-7} = rd; 360 let Opcode = opcode.Value; 361} 362 363class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode, 364 dag outs, dag ins, string opcodestr, string argstr> 365 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 366 bits<5> shamt; 367 bits<5> rs1; 368 bits<5> rd; 369 370 let Inst{31-25} = imm11_5; 371 let Inst{24-20} = shamt; 372 let Inst{19-15} = rs1; 373 let Inst{14-12} = funct3; 374 let Inst{11-7} = rd; 375 let Opcode = opcode.Value; 376} 377 378class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 379 string opcodestr, string argstr> 380 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> { 381 bits<12> imm12; 382 bits<5> rs2; 383 bits<5> rs1; 384 385 let Inst{31-25} = imm12{11-5}; 386 let Inst{24-20} = rs2; 387 let Inst{19-15} = rs1; 388 let Inst{14-12} = funct3; 389 let Inst{11-7} = imm12{4-0}; 390 let Opcode = opcode.Value; 391} 392 393class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 394 string opcodestr, string argstr> 395 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> { 396 bits<12> imm12; 397 bits<5> rs2; 398 bits<5> rs1; 399 400 let Inst{31} = imm12{11}; 401 let Inst{30-25} = imm12{9-4}; 402 let Inst{24-20} = rs2; 403 let Inst{19-15} = rs1; 404 let Inst{14-12} = funct3; 405 let Inst{11-8} = imm12{3-0}; 406 let Inst{7} = imm12{10}; 407 let Opcode = opcode.Value; 408} 409 410class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 411 string argstr> 412 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> { 413 bits<20> imm20; 414 bits<5> rd; 415 416 let Inst{31-12} = imm20; 417 let Inst{11-7} = rd; 418 let Opcode = opcode.Value; 419} 420 421class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 422 string argstr> 423 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> { 424 bits<20> imm20; 425 bits<5> rd; 426 427 let Inst{31} = imm20{19}; 428 let Inst{30-21} = imm20{9-0}; 429 let Inst{20} = imm20{10}; 430 let Inst{19-12} = imm20{18-11}; 431 let Inst{11-7} = rd; 432 let Opcode = opcode.Value; 433} 434 435//===----------------------------------------------------------------------===// 436// Instruction classes for .insn directives 437//===----------------------------------------------------------------------===// 438 439class DirectiveInsnR<dag outs, dag ins, string argstr> 440 : RVInst<outs, ins, "", "", [], InstFormatR> { 441 bits<7> opcode; 442 bits<7> funct7; 443 bits<3> funct3; 444 445 bits<5> rs2; 446 bits<5> rs1; 447 bits<5> rd; 448 449 let Inst{31-25} = funct7; 450 let Inst{24-20} = rs2; 451 let Inst{19-15} = rs1; 452 let Inst{14-12} = funct3; 453 let Inst{11-7} = rd; 454 let Opcode = opcode; 455 456 let AsmString = ".insn r " # argstr; 457} 458 459class DirectiveInsnR4<dag outs, dag ins, string argstr> 460 : RVInst<outs, ins, "", "", [], InstFormatR4> { 461 bits<7> opcode; 462 bits<2> funct2; 463 bits<3> funct3; 464 465 bits<5> rs3; 466 bits<5> rs2; 467 bits<5> rs1; 468 bits<5> rd; 469 470 let Inst{31-27} = rs3; 471 let Inst{26-25} = funct2; 472 let Inst{24-20} = rs2; 473 let Inst{19-15} = rs1; 474 let Inst{14-12} = funct3; 475 let Inst{11-7} = rd; 476 let Opcode = opcode; 477 478 let AsmString = ".insn r4 " # argstr; 479} 480 481class DirectiveInsnI<dag outs, dag ins, string argstr> 482 : RVInst<outs, ins, "", "", [], InstFormatI> { 483 bits<7> opcode; 484 bits<3> funct3; 485 486 bits<12> imm12; 487 bits<5> rs1; 488 bits<5> rd; 489 490 let Inst{31-20} = imm12; 491 let Inst{19-15} = rs1; 492 let Inst{14-12} = funct3; 493 let Inst{11-7} = rd; 494 let Opcode = opcode; 495 496 let AsmString = ".insn i " # argstr; 497} 498 499class DirectiveInsnS<dag outs, dag ins, string argstr> 500 : RVInst<outs, ins, "", "", [], InstFormatS> { 501 bits<7> opcode; 502 bits<3> funct3; 503 504 bits<12> imm12; 505 bits<5> rs2; 506 bits<5> rs1; 507 508 let Inst{31-25} = imm12{11-5}; 509 let Inst{24-20} = rs2; 510 let Inst{19-15} = rs1; 511 let Inst{14-12} = funct3; 512 let Inst{11-7} = imm12{4-0}; 513 let Opcode = opcode; 514 515 let AsmString = ".insn s " # argstr; 516} 517 518class DirectiveInsnB<dag outs, dag ins, string argstr> 519 : RVInst<outs, ins, "", "", [], InstFormatB> { 520 bits<7> opcode; 521 bits<3> funct3; 522 523 bits<12> imm12; 524 bits<5> rs2; 525 bits<5> rs1; 526 527 let Inst{31} = imm12{11}; 528 let Inst{30-25} = imm12{9-4}; 529 let Inst{24-20} = rs2; 530 let Inst{19-15} = rs1; 531 let Inst{14-12} = funct3; 532 let Inst{11-8} = imm12{3-0}; 533 let Inst{7} = imm12{10}; 534 let Opcode = opcode; 535 536 let AsmString = ".insn b " # argstr; 537} 538 539class DirectiveInsnU<dag outs, dag ins, string argstr> 540 : RVInst<outs, ins, "", "", [], InstFormatU> { 541 bits<7> opcode; 542 543 bits<20> imm20; 544 bits<5> rd; 545 546 let Inst{31-12} = imm20; 547 let Inst{11-7} = rd; 548 let Opcode = opcode; 549 550 let AsmString = ".insn u " # argstr; 551} 552 553class DirectiveInsnJ<dag outs, dag ins, string argstr> 554 : RVInst<outs, ins, "", "", [], InstFormatJ> { 555 bits<7> opcode; 556 557 bits<20> imm20; 558 bits<5> rd; 559 560 let Inst{31-12} = imm20; 561 let Inst{11-7} = rd; 562 let Opcode = opcode; 563 564 let AsmString = ".insn j " # argstr; 565} 566