1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines an instruction selector for the RISCV target. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H 15 16 #include "RISCV.h" 17 #include "RISCVTargetMachine.h" 18 #include "llvm/CodeGen/SelectionDAGISel.h" 19 20 // RISCV-specific code to select RISCV machine instructions for 21 // SelectionDAG operations. 22 namespace llvm { 23 class RISCVDAGToDAGISel : public SelectionDAGISel { 24 const RISCVSubtarget *Subtarget = nullptr; 25 26 public: 27 explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine) 28 : SelectionDAGISel(TargetMachine) {} 29 30 StringRef getPassName() const override { 31 return "RISCV DAG->DAG Pattern Instruction Selection"; 32 } 33 34 bool runOnMachineFunction(MachineFunction &MF) override { 35 Subtarget = &MF.getSubtarget<RISCVSubtarget>(); 36 return SelectionDAGISel::runOnMachineFunction(MF); 37 } 38 39 void PostprocessISelDAG() override; 40 41 void Select(SDNode *Node) override; 42 43 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 44 std::vector<SDValue> &OutOps) override; 45 46 bool SelectAddrFI(SDValue Addr, SDValue &Base); 47 48 bool MatchSRLIW(SDNode *N) const; 49 bool MatchSLLIUW(SDNode *N) const; 50 51 bool selectVLOp(SDValue N, SDValue &VL); 52 53 bool selectVSplat(SDValue N, SDValue &SplatVal); 54 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal); 55 bool selectVSplatUimm5(SDValue N, SDValue &SplatVal); 56 57 void selectVLSEG(SDNode *Node, unsigned IntNo, bool IsStrided); 58 void selectVLSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided); 59 void selectVLSEGFF(SDNode *Node); 60 void selectVLSEGFFMask(SDNode *Node); 61 void selectVLXSEG(SDNode *Node, unsigned IntNo); 62 void selectVLXSEGMask(SDNode *Node, unsigned IntNo); 63 void selectVSSEG(SDNode *Node, unsigned IntNo, bool IsStrided); 64 void selectVSSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided); 65 void selectVSXSEG(SDNode *Node, unsigned IntNo); 66 void selectVSXSEGMask(SDNode *Node, unsigned IntNo); 67 68 // Include the pieces autogenerated from the target description. 69 #include "RISCVGenDAGISel.inc" 70 71 private: 72 void doPeepholeLoadStoreADDI(); 73 }; 74 } 75 76 #endif 77