15ffd83dbSDimitry Andric //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===// 25ffd83dbSDimitry Andric // 35ffd83dbSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 45ffd83dbSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 55ffd83dbSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 65ffd83dbSDimitry Andric // 75ffd83dbSDimitry Andric //===----------------------------------------------------------------------===// 85ffd83dbSDimitry Andric // 95ffd83dbSDimitry Andric // This file defines an instruction selector for the RISCV target. 105ffd83dbSDimitry Andric // 115ffd83dbSDimitry Andric //===----------------------------------------------------------------------===// 125ffd83dbSDimitry Andric 135ffd83dbSDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H 145ffd83dbSDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H 155ffd83dbSDimitry Andric 165ffd83dbSDimitry Andric #include "RISCV.h" 175ffd83dbSDimitry Andric #include "RISCVTargetMachine.h" 185ffd83dbSDimitry Andric #include "llvm/CodeGen/SelectionDAGISel.h" 195ffd83dbSDimitry Andric 205ffd83dbSDimitry Andric // RISCV-specific code to select RISCV machine instructions for 215ffd83dbSDimitry Andric // SelectionDAG operations. 225ffd83dbSDimitry Andric namespace llvm { 235ffd83dbSDimitry Andric class RISCVDAGToDAGISel : public SelectionDAGISel { 245ffd83dbSDimitry Andric const RISCVSubtarget *Subtarget = nullptr; 255ffd83dbSDimitry Andric 265ffd83dbSDimitry Andric public: 275ffd83dbSDimitry Andric explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine) 285ffd83dbSDimitry Andric : SelectionDAGISel(TargetMachine) {} 295ffd83dbSDimitry Andric 305ffd83dbSDimitry Andric StringRef getPassName() const override { 315ffd83dbSDimitry Andric return "RISCV DAG->DAG Pattern Instruction Selection"; 325ffd83dbSDimitry Andric } 335ffd83dbSDimitry Andric 345ffd83dbSDimitry Andric bool runOnMachineFunction(MachineFunction &MF) override { 355ffd83dbSDimitry Andric Subtarget = &MF.getSubtarget<RISCVSubtarget>(); 365ffd83dbSDimitry Andric return SelectionDAGISel::runOnMachineFunction(MF); 375ffd83dbSDimitry Andric } 385ffd83dbSDimitry Andric 395ffd83dbSDimitry Andric void PostprocessISelDAG() override; 405ffd83dbSDimitry Andric 415ffd83dbSDimitry Andric void Select(SDNode *Node) override; 425ffd83dbSDimitry Andric 435ffd83dbSDimitry Andric bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 445ffd83dbSDimitry Andric std::vector<SDValue> &OutOps) override; 455ffd83dbSDimitry Andric 465ffd83dbSDimitry Andric bool SelectAddrFI(SDValue Addr, SDValue &Base); 475ffd83dbSDimitry Andric 48*979e22ffSDimitry Andric bool SelectSLOI(SDValue N, SDValue &RS1, SDValue &Shamt); 49*979e22ffSDimitry Andric bool SelectSROI(SDValue N, SDValue &RS1, SDValue &Shamt); 50*979e22ffSDimitry Andric bool SelectRORI(SDValue N, SDValue &RS1, SDValue &Shamt); 51*979e22ffSDimitry Andric bool SelectSLLIUW(SDValue N, SDValue &RS1, SDValue &Shamt); 52*979e22ffSDimitry Andric bool SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt); 53*979e22ffSDimitry Andric bool SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt); 54*979e22ffSDimitry Andric bool SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt); 55*979e22ffSDimitry Andric bool SelectFSRIW(SDValue N, SDValue &RS1, SDValue &RS2, SDValue &Shamt); 56*979e22ffSDimitry Andric 575ffd83dbSDimitry Andric // Include the pieces autogenerated from the target description. 585ffd83dbSDimitry Andric #include "RISCVGenDAGISel.inc" 595ffd83dbSDimitry Andric 605ffd83dbSDimitry Andric private: 615ffd83dbSDimitry Andric void doPeepholeLoadStoreADDI(); 625ffd83dbSDimitry Andric }; 635ffd83dbSDimitry Andric } 645ffd83dbSDimitry Andric 655ffd83dbSDimitry Andric #endif 66