1//===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the RISC-V architecture. 10// 11//===----------------------------------------------------------------------===// 12 13// The RISC-V calling convention is handled with custom code in 14// RISCVISelLowering.cpp (CC_RISCV). 15 16def CSR_ILP32E_LP64E : CalleeSavedRegs<(add X1, X8, X9)>; 17 18def CSR_ILP32_LP64 19 : CalleeSavedRegs<(add CSR_ILP32E_LP64E, (sequence "X%u", 18, 27))>; 20 21def CSR_ILP32F_LP64F 22 : CalleeSavedRegs<(add CSR_ILP32_LP64, 23 F8_F, F9_F, (sequence "F%u_F", 18, 27))>; 24 25def CSR_ILP32D_LP64D 26 : CalleeSavedRegs<(add CSR_ILP32_LP64, 27 F8_D, F9_D, (sequence "F%u_D", 18, 27))>; 28 29defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31), 30 V2M2, V4M2, V6M2, V24M2, V26M2, V28M2, V30M2, 31 V4M4, V24M4, V28M4, V24M8); 32 33def CSR_ILP32_LP64_V 34 : CalleeSavedRegs<(add CSR_ILP32_LP64, CSR_V)>; 35 36def CSR_ILP32F_LP64F_V 37 : CalleeSavedRegs<(add CSR_ILP32F_LP64F, CSR_V)>; 38 39def CSR_ILP32D_LP64D_V 40 : CalleeSavedRegs<(add CSR_ILP32D_LP64D, CSR_V)>; 41 42// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask() 43def CSR_NoRegs : CalleeSavedRegs<(add)>; 44 45def CSR_IPRA : CalleeSavedRegs<(add X1)>; 46 47// Interrupt handler needs to save/restore all registers that are used, 48// both Caller and Callee saved registers. 49def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 31))>; 50 51// Same as CSR_Interrupt, but including all 32-bit FP registers. 52def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, 53 (sequence "F%u_F", 0, 31))>; 54 55// Same as CSR_Interrupt, but including all 64-bit FP registers. 56def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, 57 (sequence "F%u_D", 0, 31))>; 58 59// Same as CSR_Interrupt, but including all vector registers. 60def CSR_XLEN_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, 61 (sequence "V%u", 0, 31))>; 62 63// Same as CSR_Interrupt, but including all 32-bit FP registers and all vector 64// registers. 65def CSR_XLEN_F32_V_Interrupt: CalleeSavedRegs<(add CSR_XLEN_F32_Interrupt, 66 (sequence "V%u", 0, 31))>; 67 68// Same as CSR_Interrupt, but including all 64-bit FP registers and all vector 69// registers. 70def CSR_XLEN_F64_V_Interrupt: CalleeSavedRegs<(add CSR_XLEN_F64_Interrupt, 71 (sequence "V%u", 0, 31))>; 72 73// Same as CSR_Interrupt, but excluding X16-X31. 74def CSR_Interrupt_RVE : CalleeSavedRegs<(sub CSR_Interrupt, 75 (sequence "X%u", 16, 31))>; 76 77// Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31. 78def CSR_XLEN_F32_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_Interrupt, 79 (sequence "X%u", 16, 31))>; 80 81// Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31. 82def CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt, 83 (sequence "X%u", 16, 31))>; 84 85// Same as CSR_XLEN_V_Interrupt, but excluding X16-X31. 86def CSR_XLEN_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_V_Interrupt, 87 (sequence "X%u", 16, 31))>; 88 89// Same as CSR_XLEN_F32_V_Interrupt, but excluding X16-X31. 90def CSR_XLEN_F32_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_V_Interrupt, 91 (sequence "X%u", 16, 31))>; 92 93// Same as CSR_XLEN_F64_V_Interrupt, but excluding X16-X31. 94def CSR_XLEN_F64_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_V_Interrupt, 95 (sequence "X%u", 16, 31))>; 96 97def CSR_RT_MostRegs : CalleeSavedRegs<(sub CSR_Interrupt, X6, X7, X28)>; 98def CSR_RT_MostRegs_RVE : CalleeSavedRegs<(sub CSR_RT_MostRegs, 99 (sequence "X%u", 16, 31))>; 100