1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15def FeatureStdExtM 16 : SubtargetFeature<"m", "HasStdExtM", "true", 17 "'M' (Integer Multiplication and Division)">; 18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19 AssemblerPredicate<(all_of FeatureStdExtM), 20 "'M' (Integer Multiplication and Division)">; 21 22def FeatureStdExtA 23 : SubtargetFeature<"a", "HasStdExtA", "true", 24 "'A' (Atomic Instructions)">; 25def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 26 AssemblerPredicate<(all_of FeatureStdExtA), 27 "'A' (Atomic Instructions)">; 28 29def FeatureStdExtF 30 : SubtargetFeature<"f", "HasStdExtF", "true", 31 "'F' (Single-Precision Floating-Point)">; 32def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 33 AssemblerPredicate<(all_of FeatureStdExtF), 34 "'F' (Single-Precision Floating-Point)">; 35 36def FeatureStdExtD 37 : SubtargetFeature<"d", "HasStdExtD", "true", 38 "'D' (Double-Precision Floating-Point)", 39 [FeatureStdExtF]>; 40def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 41 AssemblerPredicate<(all_of FeatureStdExtD), 42 "'D' (Double-Precision Floating-Point)">; 43 44def FeatureStdExtC 45 : SubtargetFeature<"c", "HasStdExtC", "true", 46 "'C' (Compressed Instructions)">; 47def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 48 AssemblerPredicate<(all_of FeatureStdExtC), 49 "'C' (Compressed Instructions)">; 50 51def FeatureExtZbb 52 : SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true", 53 "'Zbb' (Base 'B' Instructions)">; 54def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, 55 AssemblerPredicate<(all_of FeatureExtZbb), 56 "'Zbb' (Base 'B' Instructions)">; 57 58def FeatureExtZbc 59 : SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true", 60 "'Zbc' (Carry-Less 'B' Instructions)">; 61def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, 62 AssemblerPredicate<(all_of FeatureExtZbc), 63 "'Zbc' (Carry-Less 'B' Instructions)">; 64 65def FeatureExtZbe 66 : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", 67 "'Zbe' (Extract-Deposit 'B' Instructions)">; 68def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, 69 AssemblerPredicate<(all_of FeatureExtZbe), 70 "'Zbe' (Extract-Deposit 'B' Instructions)">; 71 72def FeatureExtZbf 73 : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", 74 "'Zbf' (Bit-Field 'B' Instructions)">; 75def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, 76 AssemblerPredicate<(all_of FeatureExtZbf), 77 "'Zbf' (Bit-Field 'B' Instructions)">; 78 79def FeatureExtZbm 80 : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", 81 "'Zbm' (Matrix 'B' Instructions)">; 82def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, 83 AssemblerPredicate<(all_of FeatureExtZbm), 84 "'Zbm' (Matrix 'B' Instructions)">; 85 86def FeatureExtZbp 87 : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true", 88 "'Zbp' (Permutation 'B' Instructions)">; 89def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, 90 AssemblerPredicate<(all_of FeatureExtZbp), 91 "'Zbp' (Permutation 'B' Instructions)">; 92 93def FeatureExtZbr 94 : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", 95 "'Zbr' (Polynomial Reduction 'B' Instructions)">; 96def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, 97 AssemblerPredicate<(all_of FeatureExtZbr), 98 "'Zbr' (Polynomial Reduction 'B' Instructions)">; 99 100def FeatureExtZbs 101 : SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true", 102 "'Zbs' (Single-Bit 'B' Instructions)">; 103def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, 104 AssemblerPredicate<(all_of FeatureExtZbs), 105 "'Zbs' (Single-Bit 'B' Instructions)">; 106 107def FeatureExtZbt 108 : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true", 109 "'Zbt' (Ternary 'B' Instructions)">; 110def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, 111 AssemblerPredicate<(all_of FeatureExtZbt), 112 "'Zbt' (Ternary 'B' Instructions)">; 113 114// Some instructions belong to both the basic and the permutation 115// subextensions. They should be enabled if either has been specified. 116def HasStdExtZbbOrZbp 117 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">, 118 AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp)>; 119 120def FeatureExtZbproposedc 121 : SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true", 122 "'Zbproposedc' (Proposed Compressed 'B' Instructions)">; 123def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">, 124 AssemblerPredicate<(all_of FeatureExtZbproposedc), 125 "'Zbproposedc' (Proposed Compressed 'B' Instructions)">; 126 127def FeatureStdExtB 128 : SubtargetFeature<"experimental-b", "HasStdExtB", "true", 129 "'B' (Bit Manipulation Instructions)", 130 [FeatureExtZbb, 131 FeatureExtZbc, 132 FeatureExtZbe, 133 FeatureExtZbf, 134 FeatureExtZbm, 135 FeatureExtZbp, 136 FeatureExtZbr, 137 FeatureExtZbs, 138 FeatureExtZbt]>; 139def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, 140 AssemblerPredicate<(all_of FeatureStdExtB), 141 "'B' (Bit Manipulation Instructions)">; 142 143def FeatureNoRVCHints 144 : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", 145 "Disable RVC Hint Instructions.">; 146def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 147 AssemblerPredicate<(all_of(not FeatureNoRVCHints)), 148 "RVC Hint Instructions">; 149 150def FeatureStdExtV 151 : SubtargetFeature<"experimental-v", "HasStdExtV", "true", 152 "'V' (Vector Instructions)", 153 [FeatureStdExtF]>; 154def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, 155 AssemblerPredicate<(all_of FeatureStdExtV), 156 "'V' (Vector Instructions)">; 157 158def Feature64Bit 159 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 160def IsRV64 : Predicate<"Subtarget->is64Bit()">, 161 AssemblerPredicate<(all_of Feature64Bit), 162 "RV64I Base Instruction Set">; 163def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 164 AssemblerPredicate<(all_of (not Feature64Bit)), 165 "RV32I Base Instruction Set">; 166 167def RV64 : HwMode<"+64bit">; 168def RV32 : HwMode<"-64bit">; 169 170def FeatureRV32E 171 : SubtargetFeature<"e", "IsRV32E", "true", 172 "Implements RV32E (provides 16 rather than 32 GPRs)">; 173def IsRV32E : Predicate<"Subtarget->isRV32E()">, 174 AssemblerPredicate<(all_of FeatureRV32E)>; 175 176def FeatureRelax 177 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 178 "Enable Linker relaxation.">; 179 180foreach i = {1-31} in 181 def FeatureReserveX#i : 182 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", 183 "true", "Reserve X"#i>; 184 185def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", 186 "true", "Enable save/restore.">; 187 188//===----------------------------------------------------------------------===// 189// Named operands for CSR instructions. 190//===----------------------------------------------------------------------===// 191 192include "RISCVSystemOperands.td" 193 194//===----------------------------------------------------------------------===// 195// Registers, calling conventions, instruction descriptions. 196//===----------------------------------------------------------------------===// 197 198include "RISCVSchedule.td" 199include "RISCVRegisterInfo.td" 200include "RISCVCallingConv.td" 201include "RISCVInstrInfo.td" 202include "RISCVRegisterBanks.td" 203include "RISCVSchedRocket32.td" 204include "RISCVSchedRocket64.td" 205 206//===----------------------------------------------------------------------===// 207// RISC-V processors supported. 208//===----------------------------------------------------------------------===// 209 210def : ProcessorModel<"generic-rv32", NoSchedModel, []>; 211 212def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; 213 214def : ProcessorModel<"rocket-rv32", Rocket32Model, []>; 215 216def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit]>; 217 218def : ProcessorModel<"sifive-e31", Rocket32Model, [FeatureStdExtM, 219 FeatureStdExtA, 220 FeatureStdExtC]>; 221 222def : ProcessorModel<"sifive-u54", Rocket64Model, [Feature64Bit, 223 FeatureStdExtM, 224 FeatureStdExtA, 225 FeatureStdExtF, 226 FeatureStdExtD, 227 FeatureStdExtC]>; 228 229//===----------------------------------------------------------------------===// 230// Define the RISC-V target. 231//===----------------------------------------------------------------------===// 232 233def RISCVInstrInfo : InstrInfo { 234 let guessInstructionProperties = 0; 235} 236 237def RISCVAsmParser : AsmParser { 238 let ShouldEmitMatchRegisterAltName = 1; 239 let AllowDuplicateRegisterNames = 1; 240} 241 242def RISCVAsmWriter : AsmWriter { 243 int PassSubtarget = 1; 244} 245 246def RISCV : Target { 247 let InstructionSet = RISCVInstrInfo; 248 let AssemblyParsers = [RISCVAsmParser]; 249 let AssemblyWriters = [RISCVAsmWriter]; 250 let AllowRegisterRenaming = 1; 251} 252