1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15def FeatureStdExtM 16 : SubtargetFeature<"m", "HasStdExtM", "true", 17 "'M' (Integer Multiplication and Division)">; 18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19 AssemblerPredicate<"FeatureStdExtM">; 20 21def FeatureStdExtA 22 : SubtargetFeature<"a", "HasStdExtA", "true", 23 "'A' (Atomic Instructions)">; 24def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 25 AssemblerPredicate<"FeatureStdExtA">; 26 27def FeatureStdExtF 28 : SubtargetFeature<"f", "HasStdExtF", "true", 29 "'F' (Single-Precision Floating-Point)">; 30def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 31 AssemblerPredicate<"FeatureStdExtF">; 32 33def FeatureStdExtD 34 : SubtargetFeature<"d", "HasStdExtD", "true", 35 "'D' (Double-Precision Floating-Point)", 36 [FeatureStdExtF]>; 37def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 38 AssemblerPredicate<"FeatureStdExtD">; 39 40def FeatureStdExtC 41 : SubtargetFeature<"c", "HasStdExtC", "true", 42 "'C' (Compressed Instructions)">; 43def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 44 AssemblerPredicate<"FeatureStdExtC">; 45 46def FeatureRVCHints 47 : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true", 48 "Enable RVC Hint Instructions.">; 49def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 50 AssemblerPredicate<"FeatureRVCHints">; 51 52def Feature64Bit 53 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 54def IsRV64 : Predicate<"Subtarget->is64Bit()">, 55 AssemblerPredicate<"Feature64Bit">; 56def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 57 AssemblerPredicate<"!Feature64Bit">; 58 59def RV64 : HwMode<"+64bit">; 60def RV32 : HwMode<"-64bit">; 61 62def FeatureRV32E 63 : SubtargetFeature<"e", "IsRV32E", "true", 64 "Implements RV32E (provides 16 rather than 32 GPRs)">; 65def IsRV32E : Predicate<"Subtarget->isRV32E()">, 66 AssemblerPredicate<"FeatureRV32E">; 67 68def FeatureRelax 69 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 70 "Enable Linker relaxation.">; 71 72//===----------------------------------------------------------------------===// 73// Named operands for CSR instructions. 74//===----------------------------------------------------------------------===// 75 76include "RISCVSystemOperands.td" 77 78//===----------------------------------------------------------------------===// 79// Registers, calling conventions, instruction descriptions. 80//===----------------------------------------------------------------------===// 81 82include "RISCVRegisterInfo.td" 83include "RISCVCallingConv.td" 84include "RISCVInstrInfo.td" 85include "RISCVRegisterBanks.td" 86 87//===----------------------------------------------------------------------===// 88// RISC-V processors supported. 89//===----------------------------------------------------------------------===// 90 91def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>; 92 93def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit, 94 FeatureRVCHints]>; 95 96//===----------------------------------------------------------------------===// 97// Define the RISC-V target. 98//===----------------------------------------------------------------------===// 99 100def RISCVInstrInfo : InstrInfo { 101 let guessInstructionProperties = 0; 102} 103 104def RISCVAsmParser : AsmParser { 105 let ShouldEmitMatchRegisterAltName = 1; 106 let AllowDuplicateRegisterNames = 1; 107} 108 109def RISCVAsmWriter : AsmWriter { 110 int PassSubtarget = 1; 111} 112 113def RISCV : Target { 114 let InstructionSet = RISCVInstrInfo; 115 let AssemblyParsers = [RISCVAsmParser]; 116 let AssemblyWriters = [RISCVAsmWriter]; 117 let AllowRegisterRenaming = 1; 118} 119