1//===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15include "RISCVFeatures.td" 16 17//===----------------------------------------------------------------------===// 18// RISC-V profiles supported. 19//===----------------------------------------------------------------------===// 20 21include "RISCVProfiles.td" 22 23//===----------------------------------------------------------------------===// 24// Named operands for CSR instructions. 25//===----------------------------------------------------------------------===// 26 27include "RISCVSystemOperands.td" 28 29//===----------------------------------------------------------------------===// 30// Registers, calling conventions, instruction descriptions. 31//===----------------------------------------------------------------------===// 32 33include "RISCVRegisterInfo.td" 34include "RISCVSchedule.td" 35include "RISCVCallingConv.td" 36include "RISCVInstrInfo.td" 37include "GISel/RISCVRegisterBanks.td" 38 39//===----------------------------------------------------------------------===// 40// RISC-V macro fusions. 41//===----------------------------------------------------------------------===// 42 43include "RISCVMacroFusion.td" 44 45//===----------------------------------------------------------------------===// 46// RISC-V Scheduling Models 47//===----------------------------------------------------------------------===// 48 49include "RISCVSchedRocket.td" 50include "RISCVSchedSiFive7.td" 51include "RISCVSchedSiFiveP400.td" 52include "RISCVSchedSiFiveP600.td" 53include "RISCVSchedSyntacoreSCR1.td" 54include "RISCVSchedSyntacoreSCR3.td" 55include "RISCVSchedXiangShanNanHu.td" 56 57//===----------------------------------------------------------------------===// 58// RISC-V processors supported. 59//===----------------------------------------------------------------------===// 60 61include "RISCVProcessors.td" 62 63//===----------------------------------------------------------------------===// 64// Define the RISC-V target. 65//===----------------------------------------------------------------------===// 66 67def RISCVInstrInfo : InstrInfo { 68 let guessInstructionProperties = 0; 69} 70 71def RISCVAsmParser : AsmParser { 72 let ShouldEmitMatchRegisterAltName = 1; 73 let AllowDuplicateRegisterNames = 1; 74} 75 76def RISCVAsmWriter : AsmWriter { 77 int PassSubtarget = 1; 78} 79 80def RISCV : Target { 81 let InstructionSet = RISCVInstrInfo; 82 let AssemblyParsers = [RISCVAsmParser]; 83 let AssemblyWriters = [RISCVAsmWriter]; 84 let AllowRegisterRenaming = 1; 85} 86