1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15include "RISCVFeatures.td" 16 17//===----------------------------------------------------------------------===// 18// Named operands for CSR instructions. 19//===----------------------------------------------------------------------===// 20 21include "RISCVSystemOperands.td" 22 23//===----------------------------------------------------------------------===// 24// Registers, calling conventions, instruction descriptions. 25//===----------------------------------------------------------------------===// 26 27include "RISCVSchedule.td" 28include "RISCVRegisterInfo.td" 29include "RISCVCallingConv.td" 30include "RISCVInstrInfo.td" 31include "GISel/RISCVRegisterBanks.td" 32 33//===----------------------------------------------------------------------===// 34// RISC-V Scheduling Models 35//===----------------------------------------------------------------------===// 36 37include "RISCVSchedRocket.td" 38include "RISCVSchedSiFive7.td" 39include "RISCVSchedSyntacoreSCR1.td" 40 41//===----------------------------------------------------------------------===// 42// RISC-V processors supported. 43//===----------------------------------------------------------------------===// 44 45include "RISCVProcessors.td" 46 47//===----------------------------------------------------------------------===// 48// Define the RISC-V target. 49//===----------------------------------------------------------------------===// 50 51def RISCVInstrInfo : InstrInfo { 52 let guessInstructionProperties = 0; 53} 54 55def RISCVAsmParser : AsmParser { 56 let ShouldEmitMatchRegisterAltName = 1; 57 let AllowDuplicateRegisterNames = 1; 58} 59 60def RISCVAsmWriter : AsmWriter { 61 int PassSubtarget = 1; 62} 63 64def RISCV : Target { 65 let InstructionSet = RISCVInstrInfo; 66 let AssemblyParsers = [RISCVAsmParser]; 67 let AssemblyWriters = [RISCVAsmWriter]; 68 let AllowRegisterRenaming = 1; 69} 70